The Lake Shore Central School District is proud to announce the worldwide publication of Champions of the Sky a Symphonic Band work commissioned by High School Band Director Eric Blodgett for the Lake Shore High School Band This powerful and soaring piece was composed by internationally renowned composer and film orchestrator Rossano Galante a Grand Island native with ties to the Lake Shore community and a long-standing friendship with Lake Shore Band Director Eric Blodgett “This has been a dream in the making for many years,” said Eric Blodgett Lake Shore Central Schools Music Department Chairman and High School Band Director “I knew early on that I wanted to leave something lasting for our students and excellence of the Lake Shore Band Program Rossano was the perfect composer to bring that vision to life.” The idea for this special commission began more than a decade ago when Mr Blodgett set out to find the right composer to create a lasting musical legacy for the Lake Shore Band Program After years of inviting top-tier composers to work with the band and watching the talent and dedication of his students grow Blodgett turned to his college bandmate and University at Buffalo and USC graduate Rossano Galante whose impressive resume includes film orchestration work on some of Hollywood’s biggest blockbusters Galante was so inspired by his visit and the students he worked with during the spring of 2022 he rearranged his schedule to ensure that Lake Shore students could premiere the piece while still in high school — a rare honor “Rossano worked with our high school and middle school bands and our students made such an impression on him that he moved his projects around to make this happen sooner,” Blodgett said “That’s how special our students and our program are It’s something I’ll never forget.” Blodgett and Galante shaped a piece that reflects the spirit and strength of Lake Shore students incorporating musical elements that pay homage to the school’s mascot inspiration came from one of their own — then-freshman Bailey Burke — who offered the title Champions of the Sky a name that perfectly captured the piece’s majestic energy “Rossano and I were really struggling with the title,” Blodgett admitted “And then Bailey — just a freshman at the time — came up with Champions of the Sky no royalties for Bailey or Lake Shore — but she’ll always know she named a piece that’s now part of band repertoire worldwide.” The Lake Shore High School Band officially premiered Champions of the Sky at their 2023 Spring Concert with Galante present to hear the final product of their collaboration the true debut performance took place a few months earlier when the band performed the piece at the OrlandoFest National Music Festival in Florida where they took home the Grand Championship “It was an incredible moment,” said Blodgett “To see our students perform something that was written just for them — and then to win the Grand Championship at a national festival with that very piece — it was beyond anything I could have hoped for.” Now published globally by Alfred Music Publishing and available through major retailers including J.W Champions of the Sky will live on for generations “This is a piece that will be played by high schools and professional bands for years to come,” Blodgett said That’s something really special.” Each score and part of the piece sold will list the following: “Commissioned by the Lake Shore High School Bands and Music Boosters for their years of dedication and service Pepper’s website or by visiting https://www.youtube.com/watch?v=za2fOM1Eocg – In recognition of the importance of mental health for individuals of all ages Copyright © 2025 Ogden Newspapers of New York | https://www.observertoday.com | PO Box 391 2025 (GLOBE NEWSWIRE) -- Harfang Exploration Inc (TSX.V: HAR) (“Harfang” or the “Company”) is pleased to announce the winter diamond drill program (“Winter Drilling”) is officially underway at its recently acquired Sky Lake Gold Project located in Ontario’s Pickle Lake Gold District Drilling will focus on the Koval patented claims I’d like to thank both the Harfang and Forage Multi Drilling teams for all their hard work preparing for the drill program,” commented Rick Breger “We have completed work on the access trail and have already drilled almost 170 metres into the first hole as of the end of yesterday’s day shift.” The Sky Lake property covers 9,100 hectares and extends 27 kilometres along a well-mineralized belt of volcanic and sedimentary rocks that lie midway between the past-producing gold deposits of the Pickle Lake Gold District and the Golden Patricia gold mine to the west Ardiden Limited reported a JORC compliant inferred mineral resource at its Kasagiminnis (“Kas”) gold project totalling 110,000 ounces of gold grading 4.3 grams per tonne Kas is located approximately 6 kilometres to the northeast of the Koval deposit and is surrounded by mineral claims owned by Harfang the Pickle Lake Gold District hosts more than 3.5 million ounces of gold The Sky Lake property benefits from nearby infrastructure as the eastern edge the property flanks highway 599 and the local power transmission lines The geological environment at Sky Lake is interpreted by management to be typical of orogenic style gold mineralization of the Abitibi – greenstone-hosted quartz-sericite-biotite-sulphide and iron formation hosted gold deposits The Koval patented claims include 28 claims totalling 295 hectares within the larger 9,100-hectare land package and 1980’s intercepted near surface high-grade gold mineralization with the majority of the holes not exceeding 200 vertical metres many of these shallow drill holes were terminated while still in mineralized zones completed a helicopter-borne versatile time domain electromagnetic and horizontal magnetic gradiometer (“VTEM”) geophysical survey 809 line-kilometres were flown in a north-south direction with traverse line spacing of 100 metres and perpendicular tie line spacing of 1,000 metres The survey covered the eastern half of the property to complement a previous VTEM survey on the western half of the property while the asset was held by Tri Origin Exploration Corp The combined VTEM surveys detected numerous EM isolated anomalies Many of these anomalies are associated with strong magnetic responses which are likely to be representative of iron formations a typical host rock for gold mineralization in the Pickle Lake Gold District The Company has received all required exploration permits in connection with Winter Drilling Drilling activities will be solely on patented claims only requiring permits associated with the access road which is located on crown land (see Figure 1) Harfang is not required to obtain exploration permits that are typically required for early exploration activities Harfang respectfully acknowledges the traditional territory of the Mishkeegogamang Ojibway First Nation We recognize their enduring presence and connection to these lands which have been their home for countless generations The Company is grateful for the opportunity to work here and is committed to conducting all activities in a way that respects their rights has reviewed and approved the technical information contained in this news release Bigot is a qualified person within the meaning of National Instrument 43-101 on standards of disclosure for mineral projects is a well-financed technically driven mineral exploration company with the primary mission to discover ore deposits in Québec and Ontario The Company is managed by an experienced team of industry professionals with a proven track record of success and controls a portfolio of highly prospective projects Harfang is dedicated to best practices through engagement with all stakeholders and a commitment to the environment Rick Breger, P.Geo.President and CEOrbreger@harfangexploration.com Cautionary Statement Regarding Forward-Looking Information The information in this news release includes certain information and statements about management’s view of future events plans and prospects that constitute forward-looking statements These statements are based upon assumptions that are subject to significant risks and uncertainties Because of these risks and uncertainties and as a result of a variety of factors achievements or performance may differ materially from those anticipated and indicated by these forward-looking statements Any number of factors could cause actual results to differ materially from these forward-looking statements as well as future results Although Harfang believes that the expectations reflected in forward-looking statements are reasonable it can give no assurances that the expectations of any forward-looking statements will prove to be correct Harfang disclaims any intention and assumes no obligation to update or revise any forward-looking statements to reflect actual results changes in factors affecting such forward-looking statements or otherwise Neither the TSX Venture Exchange nor its Regulation Services Provider (as that term is defined in the policies of the TSX Venture Exchange) accepts responsibility for the adequacy or accuracy of this release Map showing the key locations of the winter drill program Taking his Shlichus to an entirely new level donated a kidney to a former IDF soldier who fought in the Yom Kippur War “Today’s incredible kidney donor from Florida the organization that arranged for the donation wrote “He arrived to the hospital this morning along with his supportive family He walked in with a huge smile on his face excited to have this opportunity to save the life of someone he never met before.” The recipient of the Shliach’s kidney is an amazing individual who has served in the IDF during the Yom Kippur War and now looks forward to leading a healthy life once again There’s a beautiful photo of him and his daughter Δdocument.getElementById( "ak_js_1" ).setAttribute( "value" Phoronix Premium allows ad-free access to the site and other features while supporting this site's continued operations The mission at Phoronix since 2004 has centered around enriching the Linux hardware experience. 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You can also contribute to Phoronix through a PayPal tip or tip via Stripe Legal Disclaimer, Privacy Policy, Cookies | Privacy Manager | Contact Copyright © 2004 - 2025 by Phoronix Media All trademarks used are properties of their respective owners Hygon is relying on AMD's 2017 Zen 1 architecture for its CPUs and gets beaten handily by all modern mainstream desktop CPUs the dual-CPU configuration scored abysmal results in Geekbench's AI benchmark The single precision score was 1,412 points The two CPUs operated at a base frequency of 3GHz flat and were paired with 64GB of memory Intel's nearly 10-year-old Skylake-based Core i7-6700HQ quad-core mobile CPU was barely any slower than the dual 32-core chips featuring a single precision score of 1,113 points half-precision score of 589 points and a quantized score of 1,394 points Row 0 - Cell 0 Single Precision ScoreHalf Precision ScoreQuantized ScoreDual Hygion 16-core CPUs1,4125311,523Core i7-6700HQ1,1135891,394Ryzen 5 7600X3,5421,6861,394Compared to a much more modern CPU the Hygon-based server rack is (expectedly) vastly outperformed by mid-range desktop CPU hardware one AMD Ryzen 5 7600X user report we pulled up scored 3,542 points in single precision representing a 2.5x to 4x performance improvement over the Hygon server CPUs despite having only a fraction of the number of cores This is why Hygon's CPUs suffer a serious performance deficit compared to all modern CPUs Hygon is a fabless Chinese-based chip maker it can't use anything beyond AMD's original Zen architecture (at least for now) which is the company's Achilles heel for competitive generational performance improvements The only way it has been able to boost performance is by adding more cores to its CPUs and adding more CPUs to its platform which does help boost multi-core performance but critically doesn't help in most other areas such as single-core IPC and latency-related bottlenecks not to mention missing out on the latest CPU instruction sets such as AVX-512 Get Tom's Hardware's best news and in-depth reviews covering news related to computer hardware such as CPUs Dynatron coolers support up to 660W for Intel Diamond Rapids and AMD Venice CPUs Intel hedges its bet for High-NA EUV with the 14A process node — an alternate Low-NA technique has identical yield and design rules Arrow Lake die shot shows off the details of Intel's chiplet-based design We had to invent a lot of what we did in the moment." Sky Lakes Medical Center nestles alongside Klamath Lake surrounded by forests in a high desert region 60 miles south of the Cascades The area is a popular recreation destination yet in October 2020 that calm was shattered by a group based halfway across the world in Russia According to the FBI and Health and Human Services Department, the hospital was one of a dozen attacked at the same time by Ryuk ransomware threat actors a group known for being able to change methods on the fly to evade detection though the recovery process took a lot longer and prompted Gaede and his colleagues to re-examine their protocols "We've gone to every single department to document what was done before we forget this," he says "We haven't even finished that playbook yet Gaede says: Make sure your partnerships with tech vendors are strong and lean on them for help And be prepared to be surprised and versatile enough to react to those unexpected effects The attack occurred just after noon on October 26 when an employee clicked on an e-mail with a link that supposedly discussed a bonus (not an unusual or unexpected e-mail and at the same time the employee's computer blinked the first encryption efforts were conducted on Windows-based systems and soon after all systems were slowing down he got the phone call from IT alerting him of the ransomware attack Gaede says they turned to their Vocera communications platform to restore functionality but everything there was encrypted within minutes "We then realized we had to shut everything down," he says.Now The 176-bed hospital had to go offline immediately taking down more than 2,500 PCs and 600 servers and halting some clinical care services alongside all of the connected care aspects of a hospital serving roughly 120,000 people in a relatively remote area Even maintenance and environmental services were affected This is where the best-laid plans often break down Hospitals can train their personnel on what to do in the event of a ransomware attack going through a number of different scenarios and if-this-then-that situations but eventually the ramifications prove too complex It's one thing to map out all the results of putting the EHR platform into a downtime mode and quite another to understand how that affects business operations such as supply chain just as the snow was beginning to come down in Oregon Gaede suddenly found out they didn't have heated sidewalks every system is not happening," he recalls and it wasn't going to be like we had planned." Gaede says hospital executives huddled quickly that morning and then went into action the health system located some 70 miles distant in Medford The hospital's insurance carrier was contacted both Cisco Talos and Kivu Consulting were helping with recovery efforts "We had to completely rebuild our network," Gaede says We had to build backups and test them first to make sure they were clean then run the [main systems] through tests to validate that they can work have it [integrate] with another system and have everything fall apart."Ironically doctors and nurses who had spent the last 18 years getting used to the EHR platform now had to go back to the old way of doing things or even jumping online to track down information or do research Copper line fax machines were back in vogue—though one literally blew up from overuse Everything was now written on paper or spreadsheets and data and messages were conveyed from one department to another by runners in what came to be called the 'sneakernet.' The hospital ran out of prescription pads and local retail outlets were swamped with requests for paper "Few of them had been trained on how to do medicine on paper," Gaede says "We went to Walmart [and] Staples and bought all the paper they had." The hospital also had to shut down its PACS system and for several days couldn't provide any imaging Gaede says they contacted Sectra/Electromek which came in and built a whole new system on the AWS cloud so that images could be read on an iPad by the following Friday (the RIS was enabled by Saturday) 3M M*Modal then came in to integrate their services for reporting the hospital restored its Epic EHR platform alongside a fully operational PACS and radiology system While things certainly weren't "normal" at that time Gaede says everyone in the hospital was able to take a deep breath and relax a bit "It was like a brand-new go live," he says though it's hard to translate that into clinical outcomes clinicians and staff were all put through the ringer The hospital's revenues and cash flow were also affected forcing executives to dip into cash on hand to make sure everyone got their paychecks Gaede says the incident will affect their business plan for about three years with more money invested in security and data protection "We were just trying to take care of our community and we had no notion that state actors were taking aim at us The potential impact to patient care and patient harm was absolutely real," he says Legacy backups from Cohesity worked as they were supposed to staff knew what they had to do or they knew how to react when they didn't know what to do "We made it a point right from the start that we would be transparent about what happened," Gaede adds And I can look back now and feel we did the right things Hopefully this will help others in the future." Eric Wicklund is the associate content manager and senior editor for Innovation at HealthLeaders Photo credit: Photo courtesy Sky Lakes Medical Center was one of a dozen health systems hit by Ryuk ransomware threat actors in October 2020 The attack forced the hospital to shut down all online services Hospital staff were able to rebuild networks and restore functions within weeks and learned valuable lessons along the way about technology and the importance of staff members with good sneakers Is the APP the answer to the CMO's workforce and budget challenges a growing tension is becoming clear: the reality of what AI can deliver versus what it can't When you’ve got a lawn overlooking Lake Michigan A big glass box in the sky may be the current standard for luxury living an apartment that read like a house was a sure sign of success dining rooms that could comfortably seat 12 wood-paneled libraries with fireplaces — rooms it didn’t get much better than the roof-filling penthouse at 1500 North Lake Shore Drive 57-unit building designed by architect Rosario Candela in 1931 A Sicilian immigrant who studied architecture at Columbia University Candela designed some of the most prestigious residential properties on New York’s Upper East Side this home is just over a third the size of Rockefeller’s but with a 39-foot-long walnut-paneled gallery and a dining room Charles Foster Kane might envy The 18-room property includes an exercise room and a study-like space complete with wet bar Designed in a style evocative of an Italian villa A long gallery overlooking the living room is backed by an elaborate grille of carved and turned millwork while a loggia and lawn (complete with fountain) afford a panoramic view over Lake Michigan Tags: Chicago magazine newsletters have you covered Share on FacebookShare on X (formerly Twitter)Share on PinterestShare on LinkedInMEMPHIS (WMC) - A double shooting in Frayser’s Sky Lake neighborhood has left one man dead and another injured Monday night Memphis police are still on the scene at Birchfield Drive and Waters Edge Drive One victim was pronounced dead on the scene The other was rushed to Regional One Hospital in critical condition No suspect information is available at this time Those with information are asked to call CrimeStoppers at 901-528-CASH Click here to sign up for our newsletter Click here to report a spelling or grammar error a low-key record from a modest North Carolina duo that immediately scans as modernist indie rock but would have been virtually inconceivable a decade ago tuneful emo and unaccountably racked up over 6 million Spotify streams despite zero mainstream coverage and a tiny touring footprint but Calvin Lauber here provides the exact opposite of that record’s piercing clarity enveloping Florida heat hangs all over Sky Lake earthy sense of place that’s rare in this mode of indie rock bolstered by the off-kilter images that dot Turner’s somnolent vocals: palm readers The third book in a series by Santa Rosa author Scott Lipanovich is a page-turning must-read “One-hundred foot Jeffrey pines lighted like fourth of July sparklers….flames jumped from tree top to tree top like electric power lines springing to life Flames blasted our closed eyes with piercing orange light I tasted blood.” Santa Rosa author Scott Lipanovich knows something about fire as we all do who live in this area only the conflagration he is describing is taking place not here but in the Lake Tahoe area “Sky Lake” is the third of a series of Jeff Taylor mysteries all of which are set in northern California Protagonist Taylor has married his girlfriend He needs to study for his licensing exam so he retreats to a soothing and less distracting area of the state while his new wife visits relatives on the east coast While casually reading a local newspaper he learns about the death of an old friend Even though Boyd and Taylor were close as young adults they had grown apart and had not been in contact for years Taylor is curious about the circumstances surrounding Boyd’s demise so on a whim he travels to the upscale community where the skier had lived called Sky Lake Upon arriving at Boyd’s cabin he is met by a unsavory character who tells him gruffly to get out which he does quickly after noticing that the guy is carrying a gun Not too long after this incident other skiers in other areas turn up dead as well Taylor takes it upon himself to find out what is going on Drugs become tangentially involved with forest fires Boyd’s former spouse is an ultra-glamorous gimlet-swilling model who would love to seduce our hero but he resists her advances while maintaining a friendship The plot unfolds against the pristine wilderness of the Tahoe area And remember Taylor is doing all his sleuthing while studying for an exam that will determine the trajectory of his career Lipanovich’s prose is not so much poetic as it is crisp Description is very visual and has visceral immediacy roads and scenic spots involved seem to be non-fictional but those of someone who is very familiar with the area Probably there will be other Jeff Taylor mysteries on the author’s agenda the second one was set in the Sacramento area and this third one Perhaps the writer will eventually bring his subject back to Santa Rosa Check your local bookstores or library branch for “Sky Lake” and other books in the Jeff Taylor series Diane McCurdy can be reached at dmccurdy@sonic.net has a BA from SF State and an MA from SSU in English Literature and several teaching credentials thus her DVD reviews on a broad spectrum of films this interest in creative imagination extends to the printed page and book reviews for those who love to read Eclypsium Automata uncovers Phoenix as the latest to fall to a significant Arbitrary Code Execution exploit impacting Lenovo The specific Phoenix SecureCore UEFI firmware vulnerability that prompted this posting is referred to as "UEFIcanhazbufferoverflow" by Eclypsium which is just a funny way of pointing out that this is a buffer overflow exploit The specific method in which the "UEFIcanhazbufferoverflow" exploit works is by using an unsafe call to the "GetVariable" UEFI service allowing for arbitrary code to be executed even a buffer overflow allows for full-system access and control to be gained very quickly and the consequences of that happening can be challenging to remove from a PC permanently it may even be impossible without replacing the machine entirely— and that's not counting passwords and such that may become compromised and still need changing between machines Any potentially impacted Intel user should update their BIOS to protect from this issue as soon as possible though not before creating backups of important files and the original BIOS just in case something goes wrong Since exploits impacting UEFI are as close to Layer 0 as they get with PC hardware it's essential for all parties involved to act as quickly and safely as possible it's always nice to see cutting-edge AI and machine learning tech put toward something useful for humanity Christopher HarperContributing WriterChristopher Harper has been a successful freelance tech writer specializing in PC hardware and gaming since 2015 and ghostwrote for various B2B clients in High School before that Christopher is best known to friends and rivals as an active competitive player in various eSports (particularly fighting games and arena shooters) and a purveyor of music ranging from Jimi Hendrix to Killer Mike to the Sonic Adventure 2 soundtrack Members of a Windsor church can watch ducks paddle on Sky Lake hear geese honk overhead and see chipmunks rustle through the leaves during Sunday services which holds outdoor services at Sky Lake Camp and Retreat Center in Windsor on Sunday afternoons from April through December “We are focused on connecting with and caring for creation,” said the Rev Services are held on the shores of Sky Lake “Our service is a lot more conversational,” she said “We invite people to ask questions and share their perspectives and thoughts.” Part of the service allows worshippers to simply sit and enjoy the natural beauty around them “We just try to soak it up and be in it for a while.” birds will sit right down in the middle of the circle,” she said Brave chipmunks have rustled the leaves and come over for a closer look while shyer ones have scurried past Church members have seen a blue heron so many times that they consider it the church’s mascot More: This clothing giveaway helped JC church members 'build a bridge to our neighbors' “We really feel we have a lot to learn from creation and from our more than human neighbors — the plants and animals that are with us in our worship,” she said “We do try to look at them and learn from their wisdom.”    church members gather inside the lodge at Sky Lake Church members go outside to gather what they can for the altar including logs for the fire “We still feel very connected to nature,” she said “We do find ways of keeping worship wild.” services were conducted in the chapel of the Unitarian Universalist Congregation of Binghamton Services are resuming at Sky Lake this month While she is an ordained United Methodist minister “We welcome people from any denomination and any faith." Church in the Wild strives to be an alternative to traditional worship and a way to bring people together “We understand everybody comes in with their own beliefs and backgrounds,” she said “We really have enjoyed learning from each other and exploring various traditions.” Worshippers can even get a ride to Sky Lake if they need it “If you’re on the way from Endicott to Windsor the church focuses on acts of charity such as sponsoring a monthly free laundry night at a Binghamton church Church members also work with other community organizations who are connected with nature and the environment including VINES (Volunteers Improving Neighborhood Environments) and Binghamton Food Rescue “We love to partner with and help other community organizations,” she said “We’re happy partners in the work of social justice.”    at Sky Lake Camp and Retreat Center in Windsor starting in April If you need help with laundry: Church in the Wild sponsors a free laundry night from 5-8 p.m on the fourth Tuesday of each month at Leroy Coin Laundry send an email faithpressconnects@gmail.com From the 9,496-foot summit of Mount McLoughlin the Sky Lakes Wilderness spreads out like a collection of blue footprints in the forest below The more than 85 lakes in this wilderness area northeast of Medford come in sizes both large and small are nestled below sheer cliffs and in wildflower valleys and together constitute the most popular area for backpacking in the southern Cascades July and August bring the largest crowds to the Sky Lakes but between the roving gangs of mosquitoes and sometimes boiling temperatures this isn't always the most enjoyable time of year The mosquitoes disappear as quickly as the crowds after Labor Day and backpackers can wander through glacier-carved basins and across high mountain peaks in near solitude until and takes at least five hours in most circumstances no competition for campsites and a forest colored in autumn's reds Here are a few of the best options for exploring the Sky Lakes day-hikes and even a mountain climb to the highest peak in southern Oregon Directions to each trailhead are listed below For more detailed information on each hike see "100 Hikes in Southern Oregon" by William L Sullivan or "Hiking Oregon's Southern Cascades & Siskiyous" by Art Bernstein A 14-mile loop that climbs over Devil's Peak and down through the Seven Lakes Basin might well be the most scenic backpacking tour in the southern Cascades Beginning at the Seven Lakes Trailhead outside Butte Falls the trail climbs 5.3 miles and 2,400 feet up a spectacular trail to Devil's Peak where the lakes basin spreads out on one side and Upper Klamath Lake Mount McLoughlin and the abyss of Southeastern Oregon are visible on the other There are a few nice tent spots near the summit that provide the chance to watch both the sunset and sunrise from your tent the trail drops into the Seven Lakes Basin itself while the strange and pretty Alta Lake spreads out so long and skinny a person could be fooled into thinking it's a river follow Highway 62 north for 15 miles to Butte Falls Highway and turn right Follow the highway for 15 miles into the town of Butte Falls turn left at a pointer for Prospect Highway and follow it for nine miles Turn right onto Lodgepole Road 34 for eight miles and continue straight onto Road 37 follow gravel Road 3780 for four miles to a large and obvious trailhead parking area There are 13 different clear blue pools in the namesake basin of the Sky Lakes Wilderness the trails runs an easy 2.8 miles to the lower Sky Lakes Basin home to a loop that takes you past eight forested lakes The best fishing can be found at Isherwood Lake Better scenery and more fishing opportunities can be found another 1.7 miles up the trail in the Upper Sky Lakes Basin Trapper Lake and Margurette Lake sit below the sheer cliffs of Luther Mountain and make the prettiest places to set up camp for the night drive east on Highway 140 (following pointers for Klamath Falls) to mile marker 43 Turn left at a pointer for Cold Springs Trailhead and follow it (Road 3651) for 10 miles to its end at a primitive campsite and trailhead The quietest and most peaceful of the three basins is filled with blue lakes and silver cliffs It's also home to the Sky Lakes' best day-hike the trail drops a gradual two miles to Blue Lake a spectacular spot for an afternoon of lunch and fishing Just 0.8 mile up the trail is Horseshoe Lake The drive to the trailhead is wonderful as well taking in views from every direction and including some of the best vistas of Mount McLoughlin consider lodging in the nearby town of Shady Cove at the Historic Prospect Hotel or at Union Creek Resort Turn right onto Lodgepole Road 34 for eight miles and continue straight onto Road 37 for 5.3 miles of pavement and two miles of gravel turn left on gravel road 3770 for five miles to a trailhead on your right Ascending to the highest point in southern Oregon is not easy by any stretch but the fact that it doesn't require any technical climbing and follows a fairly simple route to the summit makes this one of the more popular Cascade peaks for average climbers The hike is 11 miles round-trip with roughly 4,000 feet of climb which means you'll want to be in good shape before giving it a try The route climbs 4.1 miles up a well-established trail the route gets steeper as it follows the ridgeline 1,200 feet to a summit that looks down upon the blue footprints of the Sky Lakes Wilderness on Road 3661 before veering left onto 3650 and a large and well-established trailhead Location: Southern Cascade MountainsClosest town: Medford which is an approximately 230-mile drive down Interstate 5 south about a four-hour drive from Salem.Area: 116,300 acresEstablished as wilderness: 1984Forest designation: Rogue River-Siskiyou National Forest Winema National ForestInformation: High Cascades Ranger District (541) 560 3400Cool places to stay: Lake of the Woods Resort (541) 949-8300; Historic Prospect Hotel (541) 560-3565Closest towns with hotels: Prospect Klamath FallsIn a nutshell: This popular wilderness area for hiking backpacking and fishing is home to three major lake basins and the largest mountain in southern Oregon The best time for exploring this area is September and early October Intel’s 6th Generation of its Core product line, Skylake, is officially launching today. We previously saw the performance of the two high end Skylake-K 91W processors but that was limited in detail as well as product So it is today that Intel lifts the lid on the other parts from 4.5 W in mobile through Core M 45W in Skylake-H and then the 35W/65W mêlée of socketed Skylake-S parts For today's formal launch we will be taking a look at the underlying Skylake architecture which was unveiled by Intel at their recent Intel Developer Forum this August For Intel, the Skylake platform is their second swing at processors built on the 14nm process node, following the launch of Broadwell late in 2014 The main difference from Broadwell is that Skylake is marked as a substantial change in the underlying silicon introducing new features and design paradigms to adjust to the requirements that now face computing platforms in 2015-2016 even though the design of Skylake started back in 2012 Intel’s strategy since 2008 is one of tick-tock alternating between reductions in process node at the point of manufacture (which reduces die area leakage and power consumption but keeps the layout similar) and upgrades in processor architecture (improve performance which will be explained in the next few pages Typically a complete product stack of processors for Intel runs the gamut from low power to high power This also applies on the integrated graphics side In a departure from their more recent launches Intel is launching nearly their entire Skylake product stack today in one go although there are some notable exceptions All of the Core M processors are launching today as are the i3/i5/i7 models and two new Xeon mobile processors From a power perspective this means Intel is releasing everything from the 4.5W ultra-mobile Core M through the large 65W desktop models along with the previously released 91W desktop SKUs What parts that are not launching today are the Pentium/Celeron processors Intel is launching most of their 2+2 and 4+2 SKUs today with the exception of budget SKUs and some of Intel's specialized IT/workstation SKUs Meanwhile for SKUs with Intel's high end Iris and Iris Pro integrated graphics – the 2+3 and 4+4 die configurations – Intel will also be launching these at a later time For the Iris configurations Intel is staying relatively vague for the moment telling the press that we should expect to see those parts launch in Q4'15/Q1'16 the annual Consumer Electronics Expo in Las Vegas is being held in the first week of January so we imagine we should see some movement there Today's launch will also come with a small change in how Intel brands their Core M lineup of processors With the Broadwell generation Intel used a mix of 4 and 5 character product identifiers However for the Skylake generation the Core M naming scheme is being altered to better align with Intel's existing mainstream Core i-series parts and hopefully cut down on some of the confusion in the process i5 and i7 already used on Intel's more powerful processors This will be represented by both Intel and the OEMs when it comes down to device design to afford greater differentiation in the Core M product line there will be desktop motherboard manufacturers announcing motherboards based on H170 although which of these will be available when (for both desktop and other use) is not known We have been told that the business oriented chipsets (B150/Q1x0) will have information available today but won’t necessarily ‘launch’ We have information on these later in the review As a result of all these processor and chipset families coming to market at once as well as linking up the launch to the Internationale Funkausstellung Berlin (IFA) show held in Berlin Intel’s launch is going to be joined by a number of OEMs releasing devices as well Over the course of IFA this week (we have Andrei on site) HP and others to either announce or release their devices based around Skylake We covered a number of devices back at Computex in June advertised as having ‘6th Generation’ processors so these might also start to see the light of day with regards to specifications the processor base designs come from five dies in four different packages ‘Skylake-H’ and ‘Skylake-S’ are used as easy referrals and loosely define the power consumption and end product that these go in but at the end of the day the YUHS designation can specifically segregate the size of the package (the PCB on which the die and other silicon sits) The YUHS processors all feature the same underlying cores The best way to refer to these arrangements is by the die orientation This designation means the number of cores (2 or 4) and the level of graphics (2 or 3e or 4e) it can depend highly on the device manufacturer as to the end performance you might receive and we cover this later in this article.  By virtue of the desire to reduce the number of packages in these devices the chipset/IO is integrated on the package DRAM support for Skylake-Y will be limited to LPDDR3/DDR3L and will not include DDR4 support like the others We suspect this is either for power reasons or because DDR4 needs more pins but when DDR4L comes to play we should see future Core M platforms migrate in that direction Skylake-U also follows a similar path to previous Intel generations What is new comes down to the configurations – 2+2 as expected but also 2+3e models will be available later in the year The extra ‘e’ means that these versions will also include Intel’s eDRAM solution which we have seen to be significantly useful when it comes to graphics performance.  In previous eDRAM designs this was only in available in 128MB variants but for Skylake-U we will start to see 64MB versions.  These will also be on package resulting in a 42x24mm package arrangement is typically found in high end notebooks or specific market devices such as all-in-ones where the ability to deal with the extra TDP (45W) is easier Historically the H processor family is BGA only meaning it can only be found in products soldered directly to the motherboard Intel released a handful of socketable processors for desktop/upgradeable AIO designs but with the information given above this might not happen for Skylake Skylake-H will feature 45W parts with 4+2 and 4+4e configurations the chipset is external to the processor package Some users will be disappointed that despite the move to 14nm Intel is still retaining the 2+2 and 4+2 configurations with no six-core configuration on the horizon without moving up to the high-end desktop (HEDT) platform (and back two generations in core architecture) alongside the two 91W overclocking ‘Skylake-K’ parts we have seen already Intel will launch the regular 65W parts (e.g i3-6100) and lower power ‘Skylake-T’ 45W (i7-6700T as well as varying in cache sizes and some feature sets We go more into detail over the next few pages Gallery: Intel Skylake YUHS Processor List We will go over each of the product markets in turn through this review but the gallery above showcases the 48 different processors that Intel is prepared to announce at this point This includes Pentium information as well as a few GT3e products (HD Graphics 550 48 EUs with 64MB eDRAM) that will be released over the next two quarters In a change to Intel’s previous strategy on core design disclosure we will no longer be receiving information relating to die size and transistor counts as they are no longer considered (by Intel) to be relevant to the end-user experience This data in the past might have also given Intel's compeititors more information in the public domain than ultimately they would have wanted at AnandTech we want this information – die size allows us to indicate metrics towards dies per wafer and the capable throughput of a fab producing Intel processors Transistor count is a little more esoteric In the past we have noted how proportionally more die area and transistors are being partitioned in favor of graphics and changes in that perspective can indicate the market directions that Intel deems as important Obtaining die size area is easier than transistor count as all that needs to be done is to pop off a heatspreader and bring out the calipers (then assume that there’s no frivolous extra silicon which seems counterintuitive as die area is proportional to dies per wafer and thus potential revenue) it was not clear if Intel would be providing at a minimum a set of false-color die shots with regions marked meaning that if this is not the case then when other analysts are able to do an extensive SEM analysis This is taken from our Skylake-K package analysis of the 4+2 arrangement There’s no better time to explore the Cascade Mountains in general and the Sky Lakes Wilderness in particular than during the glorious month of September The 113,849-acre wilderness in Southern Oregon is famous for its countless alpine lakes it’s filled with such dense clouds of mosquitoes that it's difficult to enjoy while the crowds thin out considerably as well If you’re looking for one last backpacking trip located just south of Crater Lake National Park you might just hear the howl of the famous wandering wolf OR-7 and his Rogue Pack The first pack of wolves to settle in Western Oregon since the 1940s makes its home in the area and a handful of people have reported hearing the mournful calls while backpacking the Sky Lakes Here are the top five hikes in this beautiful area. Each of these hikes are featured in the book “Hiking Southern Oregon,” of the Falcon Guides series This well-graded trail on the east side of the wilderness offers the chance for an easy day-hike to Puck Lake or a more ambitious trek to spectacular Snow Lakes Trail Beginning from Nannie Creek Trailhead — not far from Upper Klamath Lake — the route travels among lodgepole and ponderosa pine to Puck Lake and Little Puck Lake at mile 2.6 While there aren’t any mountain views here Puck Lake is still worthwhile due to the clarity of its water and some fun islands you can swim out to Little Puck Lake is tucked just behind its bigger brother head another 2 miles to a junction with Snow Lakes Trail (4.6 miles from Nannie Creek Trailhead) Turn left to find a full complement of tiny beautiful lakes follow OR 62 northeast for 6 miles to OR 140 at White City Turn left onto Westside Road and drive 12 miles to the well-marked Nannie Creek turnoff (FR 3484) on the left Continue 6 miles up the excellent gravel road to the trailhead The best easy hike in the Sky Lakes can be found in this very pretty canyon which has options for a longer trek and a nice drive to the trailhead Blue Canyon Trail drops through a forest of Shasta red fir mountain hemlock and western white pine to spectacular Blue Lake in just 2 miles Huge cliffs are reflected in this glassy pool and a few campgrounds can be found around the shorelines Pear and Island lakes if the mood strikes you where more campsites and better trout fishing conditions can be found The real upside of this trail is how flat the trail is compared to the next three options take OR 62 north to the Butte Falls turnoff near milepost 16 Turn right and drive 17 miles to the town of Butte Falls Continue past Butte Falls on the same road for 1 mile to the Prospect turnoff Cross the bridge and proceed 2 miles to gravel Rancheria Road Follow FR 3770 for 6 miles to the well-developed Blue Canyon Trailhead The namesake basin of this wilderness is home to no less than 14 lakes with names The main lake areas are split into two areas — Lower Sky Lakes Basin and Upper Sky Lakes Basin A grand tour of 12 to 14 miles will bring you to all of them just north of Highway 140 between Medford and Klamath Falls the mostly flat trail heads 2.8 miles into the lower basin decent for fishing and home to campgrounds but the most scenic lakes are a longer trek Follow Sky Lakes Trail another 2.6 miles to reach the upper basin highlighted by spectacular Trapper Lake and More glorious campsites can be found here and more adventure Turn right onto OR 140 and follow it east toward Klamath Falls for 41 miles a gravel road (FR 3651) leads to the left at a Cold Spring Trailhead sign Continue 10 miles up the gravel road to the Cold Spring Trailhead The step-up in difficulty brings many rewards in the Seven Lakes Basin home to the most scenic lake and most scenic viewpoint in the wilderness The ideal way to experience this area is with a 14-mile backpacking loop that climbs over Devil's Peak and down through the Seven Lakes Basin turn left at a pointer for Prospect Highway and follow it for 9 miles Turn right onto Lodgepole Road 34 for 8 miles and continue straight onto Road 37 follow gravel Road 3780 for 4 miles to a large and obvious trailhead parking area Southern Oregon's tallest mountain slices above the Rogue Valley like a gigantic pyramid that dominates the sky for miles around The hike although grueling at 10 miles with 3,777 feet of gain featuring every major peak from the Three Sisters to Mount Shasta while showcasing the thousands of tiny blue pools of the Sky Lakes Wilderness below The trail begins at a trailhead off Highway 140 near Four Mile Lake the trail is solid and easy to follow until the final mile and you can follow blazes on the rocks to the top) it's important to pay close attention on your way down Many people boot-ski down the loose rock on the way down and lose the trail Make sure to follow the ridgeline down to avoid this fate follow Highway 62 northeast for 6 miles to Highway 140 at White City Turn right onto OR 140 and drive to the Four Mile Lake turnoff (FR 3661) Turn left and proceed 3 miles to a short side road (FR 3650) on the left Follow it to a roomy trailhead parking area Zach Urness has been an outdoors writer, photographer and videographer in Oregon for seven years. He is the author of the book “Hiking Southern Oregon” and can be reached at zurness@StatesmanJournal.com or (503) 399-6801 Find him on Facebook at Zach’s Oregon Outdoors or @ZachsORoutdoors on Twitter Building a PC is an experience worth having Finding out what works with what and putting it all together is an experience and the first time always gives a sense of achievement and accomplishment even more so: trying not to break your first $500+ CPU can be akin to feeling like a surgeon especially after five years of iterative updates we are seeing something special happening in 2017 is changing its 2017 strategy in a few ways which means there is more to understand and also means it is set to release 18-core consumer processors with the new Skylake-X processors: the Core i9-7900X These throw a few curveballs into the mix which are worth walking into Intel announced its new high-end desktop (HEDT) platform code named Basin Falls There are three elements to Basin Falls: the new X299 chipset which brings a number of enhancements from the more mainstream consumer line a set of Skylake-X processors based on the Skylake-SP microarchitecture (and slightly different from the mainstream Skylake-S processors launched in 2015) from 6 cores to 18 cores reusing the Kaby Lake-S silicon launched earlier this year but with a bit more frequency and power consumption We covered all three parts in our launch pieces (linked below) One of the big criticisms from the launch of Broadwell-E was that Intel significantly increased prices over the preceding generation Nominally consumers were used to the fact that the top chip in the stack was $999 to $1099 Broadwell-E pushed the 10-core Core i7-6950X to ~$1721 in order to claim parity with the enterprise processors Users who scoffed at that price will be pleased to hear that the Skylake-X processors launching today are priced more in line with Intel's traditional HEDT chips The Core i9-7900X is the 10-core processor and set to have a tray price of $999 which means the shelf price will be around $1049-$1099 The Core i9-7900X is also the only one with a full complement of 44 PCIe lanes from the processor as Intel is restricting this feature to the higher cost parts of the stack in order to further differentiate it from the cheaper i7-7800 series This processor is quite aggressive in its specifications – normally the top LCC processor is clocked down using the extra cores as the main reason for purchase but here Intel is supporting a maximum turbo frequency of 4.3 GHz or up to 4.5 GHz with the new-ish favored core mode The base frequency is lower than the other CPUs to compensate but we saw an all-core frequency at 4.0 GHz in our testing with support up to DDR4-2666 in quad channel mode at 1 DIMM per channel (DDR4-2400 at 2DPC) exchanging two of the CPU cores and some PCIe lanes for a higher base frequency but has a base frequency of 3.6 GHz to compensate The PCIe lanes are reduced from 44 to 28 as part of Intel’s product segmentation strategy although Intel notes this is still enough for a single GPU and three PCIe 3.0 x4 devices (such as storage) directly attached to the processor DRAM support is the same as the Core i9 at DDR4-2666 Coming in at $599 represents a bit of a step from the 10-core down to the 8-core This price will arguably draw a good number of users who would rather direct that $400 to something else in their system with the only deficit being two cores and a proper x16/x16 layout for dual video cards While categorically ‘the runt’ of the litter only $50 more than the mainstream consumer quad-core overclocking processors Along with a slight cost increase for the new X299 motherboards users looking to move from the mainstream to the bottom rung of the high-end desktop can do so with around $120-$150 extra for CPU+motherboard and then a bit more if the users wants to use quad channel memory (these processors work in dual channel as well) traditionally users may point to it as a potential overclocking processor – we unfortunately did not have time to test our sample for overclocking but I wouldn’t be surprised to see it hit the same frequencies as the other two processors fairly easily Intel only had one serious angle of competition for the HEDT platform: itself the older generation could (sometimes) be picked up cheaper Intel has three main sources of competition for the X299 platform Intel’s older platform in Broadwell-E (or even Haswell-E) with extensive motherboard support and well-known functionality Intel has not officially dropped the prices of the older processors which unless the retailers decide to shift stock wholesale might discourage users going for brand new CPUs Second is AMD’s recently released Ryzen set of CPUs As the first new serious entry into the HEDT space for AMD in almost five years AMD offered similar-ish performance to Broadwell-E in many aspects (within a few percent) The Ryzen CPUs still had other limits – dual channel memory and a miasma surrounding the launch with motherboards and memory support; but several months on the ecosystem for Ryzen is fairly solid and still a new and exciting prospect for the HEDT crowd For $60 less than the price of the Core i7-7800X which runs in at 8 cores at slightly lower frequency Both Intel and AMD would argue the merits of the platforms vs but Intel still this as an angle for competition the 6-core Core i7-7820X at $599 goes up against the 8-core $499 Ryzen 7 1800X Third is AMD’s future HEDT (or Super High-End Desktop AMD is set to offer a new X399 chipset with ThreadRipper processors up to 16-core and with 60 PCIe lanes for graphics (plus four for the chipset AMD is using two of its consumer Zeppelin silicon dies on the same package to get up to 16-cores and has a new socket planned due to the increase in PCIe support Having had Intel moving from 6 to 8 to 10 cores on the HEDT space over the last 5-6 years meant that AMD announcing a 16-core part was a big enough jolt to this market such that Intel has to provide a response Pitting a 10-core CPU such as the Core i9-7900X against a 16-core AMD CPU means that AMD would win most the high-throughput heavily-threaded benchmarks despite perhaps being lower frequency and higher power sometimes it’s all about how quick you can compute AMD is set to launch the X399 platform and ThreadRipper CPUs in the summer so we’re still light on details until then there's a real risk to Intel that AMD will once again undercut Intel’s equivalent 16-core pricing by a large amount This review comes in two big meaty chunks to sink your teeth into The first part is discussing the new Skylake-X processors from silicon to design and covering some of the microarchitecture features such as AVX-512-F support and cache structure Skylake-X has some significantly different functionality to the Skylake-S core which has an impact on how software should be written to take advantage of the new features The second part is our testing and results We were lucky enough to source all three Skylake-X processors for this review and have been running some regression testing of the older processors on our new 2017 testing suite There have been some hiccups along the way though An extra morsel to run after is our IPC testing We spend some time to run tests on Skylake-S and Skylake-X to see which benchmarks benefit from the new microarchitecture design and if it really does mean anything to consumers at this stage It should be noted that Intel did not provide all the CPUs for this review All CPUs in this review are classified as engineering samples for partner testing and not for resale although they are identical to retail CPUs in performance I liked the Dell XPS 13 an awful lot when I reviewed its initial Broadwell-based iteration last year with its super-thin bezel and soft-touch interior The only major flaw was the webcam placement driven by that thin bezel Some other publications also felt that battery life wasn't what it should be but in our testing it seemed decent even if it fell short of Dell's own estimates Almost everything in that review holds true of the new device The XPS 13 got all the important basics right Once again our review model has the beautiful 3200×1800 IPS touchscreen and the same extremely narrow bezel and I'm a little surprised that other manufacturers haven't leapt on the same hardware The XPS 13 is quite a bit smaller than systems with comparable screen sizes its screen is quite a bit bigger than that of systems with the same footprint To quantify that: the XPS 13 is 11.98 inches wide The 11-inch MacBook Air is 11.8 inches wide and the 13-inch MacBook Air is 12.8 inches wide the XPS 13 is 7.88 inches deep; the Apple systems are 7.56 and 8.94 inches deep This Dell with its 13.3 inch screen is much closer in size to the Mac with an 11.6 inch screen than the one with a 13.3 inch one That diminutive size means more room on your airplane tray table It's even slightly less heft to carry around; at 2.7lbs (without touch) or 2.9lbs (with touch) it's a touch lighter than the 13-inch MacBook Air the keyboard remains competent and the touchpad remains first rate My personal preference would be to have a few more keys Home/end and page up/down are doubled up onto the cursor keys and in an ideal world they'd have a dedicated button no obvious way; it's possible that there's some unlabeled shortcut) to type the "break" key But such are the norms of modern laptop keyboards and Precision Touchpad support for the full range of Windows 10 gestures and shortcuts Surrounding all this is a palm rest covered in "soft touch paint." This feels extremely comfortable Last year I was concerned that the paint may deteriorate but I've since heard from others that it stands up well It certainly feels better than the bare metal that some other laptops use for their interiors Even with alcohol wipes I failed to get it pristine driven as it is by the narrow bezel) remains awkward to the point of near-unusability With no room at the top edge of the screen creating a peculiar worm's eye view that tends to point right up your nose but there is no circumstance in which I could ever see myself using it I'm also a little disappointed that Dell hasn't embraced Windows Hello biometric login. Although the webcam positioning would almost surely rule out facial recognition, a fingerprint sensor on the keyboard would have been good. HP's comparably priced Envy 13 manages a fingerprint reader on the keyboard The new parts to the XPS 13 are all on the inside and with this comes an increase in supported RAM—now up to 16GB—and Intel's Alpine Ridge controller Alpine Ridge provides two things: the infuriatingly named USB 3.1 generation 2—which means 10 gigabits per second rather than five—and Thunderbolt 3 These are delivered over a USB Type-C port on the machine's left-hand side replacing the mini DisplayPort of the Broadwell model assuming you have something to plug into it—generation 1 and 2 USB and even charging (though the XPS 13 does not use this for charging by default; it has a dedicated charging port and charger to match) This can drive one of the handful of new USB Type-C monitors directly and with converters it'll drive DisplayPort and HDMI screens Dell also has an adaptor that provides Ethernet and more of these port replicators/docking stations are likely to materialize On a whim I plugged it into the Microsoft Display Dock used for the Lumia 950 phone suggesting that USB Type-C may have an undesirable dark side Devices may appear to be superficially compatible with one another but they won't actually do anything when connected and the ability to use it for non-USB data (such as DisplayPort or HDMI) via the Alternate Modes feature Thunderbolt 3 is just another Alternate Mode The multi-protocol nature of the port means that the port is inevitably going to be useful for something. Maybe it'll be useful for connecting USB devices; maybe it'll be useful for connecting monitors. Maybe, if the array of Thunderbolt hardware expands, it'll be useful for more exotic things such as external video cards Whatever it turns out to be, support for both USB 3.1 generation 2 and Thunderbolt 3 means that the XPS 13 is meaningfully future-proofed. But unlike the Type-C-only Spectre x2 Dell hasn't forgotten about the present; there are two regular USB 3.1 generation 1 ports on the XPS 13 so today's hardware is also well-supported the Skylake is a bit faster than the Broadwell This time around our review system had a Core i5-6200U processor compared to the Broadwell i5-5200U at 2.2/2.7GHz The Skylake is maybe 10 to 15 percent faster in Geekbench and as much as 50 percent faster in GPU tests but not so much faster as you'd really notice Likely to be more noticeable is the disk benchmark only the top-end 512GB SSD used a PCIe interface The 128GB and 256GB versions both used (slower) SATA the 256GB has made the leap to the (faster) PCIe interface Its benchmark scores are unsurprisingly a substantial improvement Although the battery is now a little bigger at 56Wh instead of 52Wh it fared somewhat worse in our battery life testing One possibility is that the original tests were affected by Dell's adaptive brightness feature that automatically reduces the screen brightness under certain situations to extend the battery life there was nothing I could do to disable this (though I checked the brightness calibration during testing and it didn't seem to change particularly) On the one hand I do feel that the battery life could and should be a bit better especially as Dell continues to maintain that it should be best-in-class longer still if you opt for the non-touch 1920×1080 screen It lasts long enough for most of the domestic flights and international flights I take and it's more than enough for going to meetings or spending an afternoon working in a coffee shop This is battery life that's long enough so it doesn't feel intrusive I was disappointed with the awful McAfee LiveSafe bundled software The previous model XPS 13 had it too—though for some reason it didn't show me as many annoying alerts and messages—and so does this one I suggested that users uninstall it for fear that it would interfere with something I uninstalled it myself because it was so intrusive I have taken the opinion that the software is actively user hostile OEMs are doing a great user disservice by bundling it That's because it showed me this message when I opened the Edge browser The notion that Windows 10 users should switch to Internet Explorer instead of using Edge solely because Internet Explorer allows poorly secured highly invasive add-ons is beyond ridiculous This software is making a really bad suggestion it's annoying that Edge has no add-ons yet and when they do they'll be secure and restricted and sandboxed and all the good things that browser extensions should be Microsoft didn't abandon the old Internet Explorer extension model because it was good; the company abandoned it because it wasn't good For a "security" application to tell me to use the older less standards-compliant browser just to use a bad extension model is beyond the pale Although the battery life regression is something of a mystery the new XPS 13 is every bit as likeable as the old one The best bit is that even with the new processor and Thunderbolt 3 I still feel that system skimps a little too much on memory and storage prices go higher than they used to thanks to the new 16GB RAM option and a core i7 processor the XPS 13 will set you back $2,079.99 Bumping up to a 1TB SSD increases the price further still and a Core i5 processor—feels like something of a sweet spot It's still the mainstream Ultrabook to get Other systems may be superior in particular ways—360 degree hinges better webcam placement—but the XPS 13 is an extremely well-rounded package that's strong in almost every way that is unless you really need to use the webcam As part of the Intel Xeon Scalable v. AMD EPYC internal numbers that Intel has given to publications Intel is confirming the Skylake based Xeon D CPU in early 2018 We take “early” to mean that we will see the new Skylake Xeon D SoC in Q1 2018 Here is the slide from the presentation that Intel shared confirming that the new Xeon D will launch in 2018 The idea of a Skylake Xeon D launch in Q1 does not necessarily mean that you can buy a motherboard with the SoC in Q1 we see the “launch” mean launch to retail/ OEM manufacturers It then can take several weeks for systems to be updated and available for purchase in the channel If you are a large customer of the Intel Xeon D you likely will have access before the launch or have customized parts available on your customer specific timetable We would not be surprised to see smaller customers more in the Q2 timeframe For many customers, especially those looking at large edge deployments and hyper-scale style deployments, Intel needs to get the Skylake Xeon D out sooner rather than later. We have heard it suggested that the 16 core Atom C3955 is the replacement Intel needs the Skylake Xeon D part to have a unified ISA between its mainstream Xeon and SoC products That allows for things like live migrations of VMs it also allows companies to optimize binaries for caches and instruction sets and run them across embedded and mainstream servers Like with the Broadwell-DE launch expect comprehensive of Intel Xeon D Skylake edition coverage on STH Does anyone think Intel will include QuickAssist in Skylake-D similar to the Atom C3xxx family Someone (maybe STH?) was talking about testing QuickAssist with ZFS so it may be something I try to use in the future… and website in this browser for the next time I comment This site uses Akismet to reduce spam. Learn how your comment data is processed. The first thing that comes to mind with Intel’s newest line of 10th Generation desktop processors is one of ‘14nm Skylake It is hard not to ignore the elephant in the room – these new processors are minor iterative updates on Intel’s 2015 processor line moving up from four cores to ten cores and some extra frequency but by and large it is still the same architecture At a time when Intel has some strong competition Comet Lake is the holding pattern until Intel can bring its newer architectures to the desktop market Three weeks ago, Intel announced the Comet Lake 10th Generation Core processor family line for desktops From Celeron and Pentium all the way up to Core i9 there were 32 new processor models representing a sizeable offering to the market The key elements to this range of processors was the introduction of 10 cores for the Core i9 parts at the high-end – an increase of two cores over the last generation – and the introduction of Intel’s Thermal Velocity Boost for Core i9 that enables +100 MHz in the cooler thermal environments promises 5.3 GHz peak turbo in optimal conditions for two preferred cores and the Pentium Gold processors have hyperthreading making the processor stack easier to understand for this generation there are a lot of similar processor matchups the offerings should move down one price bracket this time around Intel has changed the socket for this generation, moving to an LGA1200 platform. This also means there are new motherboards, the Intel 400 series family, including the Z490 chipset which has 44+ entrants ranging from $150 all the way up to $1200. We have a very thorough analysis of every motherboard in our Z490 motherboard overview there are 32 processors for the new Comet Lake 10th Generation Core family The Core i9/i7/i5/i3 parts will broadly fall into four categories: Intel uses these divisions based on both customer demand but also its ability to separate the best quality silicon from its manufacturing Silicon that can enable low-power operation becomes T processors while silicon that can push the highest frequencies at reasonable voltages becomes the K silicon Some silicon might not be up to par with the integrated graphics and are generally cheaper than the non-F versions to the tune of $11-$25 The Core i9 and Core i7 processors will support DDR4-2933 with sixteen lanes from the CPU available for add-in cards and direct connected storage Intel likes to point out that they offer another 24 PCIe 3.0 lanes on the chipset however the uplink to the processor is still a DMI/PCIe 3.0 x4 link As far as we understand, Intel will be coming to market first with the K processors, and the other processors should be a quick follow-on. That being said, a large number of Intel’s Core 9th Gen processor line have been difficult to obtain at retail as the company sees record demand for its server processors As those command a higher operating margin Intel would rather spend its manufacturing resources making those server processors instead leading to shortages of the consumer mainline CPUs Even as a primary reviewing technology media organization focusing on companies like Intel Intel has not proactively sampled the media with many of the 9th Generation parts - perhaps the lack of availability is one of those reasons It will be interesting to see how many of the Intel 10th Gen processors are made available to both reviewers and the public alike we were able to obtain the 10-core Core i9-10900K we have multiple different levels of ‘turbo’ for every processor Intel loves to talk turbo in the sense of offering performance however it can get complicated about which levels of turbo apply at any given time and Thermal Velocity Boost without context make very little sense to anyone not necessarily au fait with the world of computer processors we can go through each of the different turbo modes into some level of specificity: Even when speaking with a number of my industry peers the way this has all been described makes it very complex and difficult to explain to each other sometimes It can be quite complex to explain to a friend why they are not seeing the maximum turbo frequency on the box for their system due to specified thermal windows that are not being achieved Intel’s Thermal Velocity Boost (TVB) limits for the i9-10900K are 5.3 GHz single core the CPU will operate somewhere above the base clock of 3.7 GHz and users will get 5.2 GHz on two favored cores (or 5.1 GHz for other cores) until the turbo budget is used and then back to somewhere above the base clock of 3.7 GHz it gets very complicated to understand exactly what frequency you might get from a processor In order to get every last MHz out of the silicon these additional qualifiers mean that users will have to pay more attention to the thermal demands of the system As explained in many of our other articles motherboard manufacturers have the option to disregard Intel’s turbo limit recommendations completely This cannot be overstated enough – at least one of my colleagues had issues with a motherboard implementing a different turbo profile than Intel’s suggested recommendations This is because with an appropriately built motherboard a manufacturer might enforce an all-core 5.1-5.3 GHz scenario with the i9-10900K for an unlimited time – if the user can cool it sufficiently Intel states that the Core i9-10900K has a peak turbo power around 250 W however motherboard manufacturers earlier this year told us they were building boards for 320-350 W turbo power to give additional thermal headroom or in the event that the 250 W suggestion is completely ignored Choosing a motherboard just got more complex if a user wants the best out of their new Comet Lake processor here is an output from our y-Cruncher test We see that the Core i9-10900K boosts uses up to 254 W at peak moments but through the whole test it uses 4.9 GHz for ~175 seconds Intel's turbo has a recommended length of 56 seconds according to the specification sheets the motherboard manfuacturer is confident that its power delivery can support a longer-than-56 second turbo time This is all above board according to Intel as they recommend that motherboard vendors apply what they think is best for the product they have built It only becomes out of specification if an overclock is applied - Intel does not consider this an overclock it’s worth pointing out the low power processors Here’s a reminder that the power consumed while in turbo mode can go above the TDP I’ve asked Intel for a sample of the processor as this is going to be a key question for the chips that have a strikingly low TDP It’s worth noting that only the Core i9 parts have Intel Thermal Velocity Boost The Core i7 hardware and below only have Turbo Max 3.0 ‘favored core’ arrangements We’ve clarified with Intel that the favored core drivers have been a part of Windows 10 since 1609 and have been mainlined into the Linux kernel since January 2017 the price saving seems to be lower for Core i9 than for any other of Intel’s segments The cost difference per-unit between the 10900K and 10900KF is only $16 we managed to secure three processors for testing: the Core i9-10900K These three 125 W processors represent the overclocking parts from each of the main categories (there is no overclockable Core i3 this generation) We tested all three processors in the ASRock Z490 PG Velocita, and the only serious issue experienced was an error completely on my part – I got fluff in the socket when changing processors The ASRock board and all three CPUs cruised through our test-suites All three CPUs are based on the 10 core silicon dies (more on the next page) which lead to some interesting core-to-core latencies which we’ll go into Unlike some of Intel’s previous parts we had no issues hitting the Thermal Velocity Boost on the Core i9-10900K as show in the CPU-Z screenshot with 5.3 GHz being registered It does look like that most motherboards are ignoring Intel’s TVB completely and making those numbers the new Turbo Boost Max 3.0 – both our system and our colleagues at other Future publications saw similar with their motherboards tested As mentioned, 10th Gen Comet Lake is, by and large, the same CPU core design as 6th Gen Skylake from 2015 and enabling more voltage/frequency customization (more on the next page) there has been no significant increase in IPC from Intel all while AMD has gone from Excavator to Zen to Zen 2 with sizable IPC increases and efficiency improvements Comet Lake does feel like another hold-over until Intel can either get its 10nm process right for the desktop market or backport its newer architectures to 14nm; so Intel should be trying its best to avoid a sixth generation of the same core design after this Comet Lake is still aiming to carve a spot in the market with the main marketing materials from Intel promising the best gaming experience Despite Intel telling us over the previous years that ‘mega-tasking’ is the new buzzword for demanding software running simultaneously on an enthusiast system with Comet Lake the messaging is back to one purpose – offering the best single-threaded gaming experience We know that AMD’s Zen 2 has as a slight 10-15% IPC advantage over 9th Gen Coffee Lake so it will be interesting to see if Intel’s 10% peak frequency advantage affords many benefits We’ll be keeping an eye on that power consumption too something that Intel users have chastised AMD hardware for in the past It’s the Intel review you’ve been waiting for Today is the launch of the first two CPUs from Intel’s Skylake architecture the 6th Generation Core i7-6700K and the Core i5-6600K With the new processors we get a new architecture the move to DDR4 and the potential to increase both performance and efficiency at the same time A lot of readers have asked the question – is it time to upgrade We had a CPU or two in to test to answer that question predicting Skylake’s launch has been a minefield some companies were discussing a large six-week window in which they expected Skylake but were waiting on official dates But as we've seen with a number of previous Intel mainstream launches Intel likes to aim at the gaming crowds release at a gaming events It just so happens that today is Gamescom in Germany two weeks before what everyone expected would be a launch at Intel’s Developer Forum in mid-August Today is a full launch for the Skylake-K processors with the two CPUs being launched alongside new Z170 series motherboards and dual channel DDR4 memory kits a number of them would have liked more stock on launch day suggesting that they expect the processors to sell out rather quickly when the buy buttons are activated ‘Where are the non-K processors?!’ you may ask Intel tells us that these will be released later in the year we have to wait and see what range of models come out at that point and we will get a number in to review To go with the launch is a new look of Intel's Core processor packaging As the gaming industry is considered one of the few remaining areas for potentially large growth in the PC industry Intel is increasing its focus on gaming as a result Aside from changing the graphics on the box it has been reported – and seemingly confirmed by the thinner boxes in the official pictures from Intel – that these processors will not be shipped with a stock Intel cooler Users will have to purchase third party coolers Part of this makes sense – overclocking processors need beefier cooling in order to extract the maximum overclock and buying something above the stock cooler should be good The downside of not having a stock cooler means an added cost to the end user However as the hole mounting for the new socket is similar to that of LGA1150/1155/1156 – spacing is still 75mm – many existing CPU coolers for the current LGA115x sockets should be compatible making it possible to reuse many coolers for no more than the cost of a new thermal paste application For users looking for a new air or liquid cooler, head on over to our recent roundup of Top Tier CPU Air Coolers Q3 2015: 9-Way Roundup Review and the Closed Loop AIO Liquid Coolers: 14-way Mega Roundup Review published last year Intel’s early issues with 14nm yields have been well documented and we won’t go into them here but 14nm is a more expensive process with an increased number of lithography steps as we reach the limits of current semiconductor technology but to move down to 10nm makes either the current process more expensive or other methods have to be used we see Moore’s Law stretching out from an 18-24 month cadence to a 24-30 month cadence for the first time in fifty years As we’ve seen with the graphics card market recently stalling at 28nm there is a need (or at least opportunity) to develop more power efficient architectures rather than just relying on die shrinks to do it for you today Skylake will hit the shelves in the form of two overclockable processors The integrated graphics nomenclature has changed with the new i7-6700K having the Intel HD 530 graphics compared to the HD4600 in the Haswell parts has 24 of Intel’s execution units in the iGPU and they run at a peak frequency of 1150 MHz The introduction of the HD 530 marks the launch of Intel’s 9th generation graphics and we'll cover Gen9 in a bit more detail later The i5 model for Skylake also has quad cores but without HyperThreading and only 6MB of L3 cache it also has the Intel HD 530 graphics but operates at a lower frequency band Both the Skylake processors will support DDR4 and DDR3L memory in order to ease the transition to DDR4 for the mainstream segment although it should be said that DDR3L is implemented here due to its lower than standard DDR3 operating voltage of 1.35 volts This more closely aligns with DDR4’s standard voltage of 1.20 volts or the high end DDR4 kits at 1.35 volts and as a result we are told that motherboards that support DDR3L will typically only be qualified to run DDR3L kits This leads onto the point that both of the K processors for Skylake sit at 91W which is a small increase over Haswell at 84W and Devil’s Canyon at 88W In the past Intel has historically run a 1:1 policy whereby a 1% performance gain must come at a maximum of a 1% power penalty – this was adjust to 2:1 for Broadwell and we should assume that Skylake had similar requirements during the planning stage Depending on the specific architecture details one potential source for this increase in power consumption may be the dual memory controller design although Skylake has a significant number of features to differentiate itself from Haswell These 2015 vintage processor iGPUs had been on legacy support since last summer Many recognize Skylake as the 6th generation of Core processors but the family launched with 9th generation iGPUs that will no longer benefit from driver updates Users of discrete graphics cards will be less worried by this EOL news avoiding the Intel graphics driver software with Skylake at the bottom of the list of generations remaining on legacy support Now that Skylake has dropped off the legacy list Kaby Lake chips are on the bottom rung of the ladder waiting to be allocated a plot in silicon heaven Intel’s 7th Gen Core Kaby Lake CPUs debuted with Intel Gen 9.5 integrated graphics as the same graphics architecture persisted through 8th supporting various editions of Windows 10 & 11 He enjoys covering the full breadth of PC tech; from business and semiconductor design to products approaching the edge of reason Intel driver update for Lunar Lake chips reportedly improves iGPU FPS by 10% AMD releases open-source GIM driver aimed at GPU virtualization support for mainstream Radeon GPUs coming later GPUs with 8GB of VRAM in 2025 are 'like bringing a butter knife to a gunfight' reckons Grok AI we discovered some interesting aspects in the design of Skylake-U systems that have a bearing on the performance of some M.2 PCIe SSDs These can affect the consumer's choice of SSDs for a Skylake-U system - be it a NUC or an user-upgradeable notebook Intel has a wide range of CPUs based on the Skylake microarchitecture These target a variety of markets ranging from tablets / 2-in-1s and Compute Sticks to the traditional tower desktops The same microarchitecture is able to serve different markets because of the scalable nature of the TDP / power envelop (from 4.5W to 91W) S- and K- CPUs need a separate Intel 100 Series platform controller hub (Sunrise Point PCH) the Skylake-U and Skylake-Y are Multi-Chip Packages (MCP) that have the Sunrise Point-LP PCH die integrated with the CPU in a single package The communication between the CPU and the PCH in the H-,S- and K- systems is via the Direct Media Interface (DMI 3.0),a proprietary link protocol developed by Intel have an On Package DMI interconnect interface termed as OPI the OPI in Skylake-U/-Y can be configured to meet the desired power or performance needs of a mobile system design The following table summarizes the differences between DMI and the two configurable OPI options in Skylake systems and this is important when a PCIe 3.0 x4 SSD is connected to the a Skylake-H/-S/-K system using PCIe lanes from the PCH Any other peripheral communicating with the CPU at the same time as the PCIe SSD would end up creating a bottleneck at the CPU-PCH link Skylake-U/-Y systems that have a PCIe 3.0 x4 SSD connected to the Sunrise Point-LP PCIe lanes will be directly impacted by the configuration of the OPI The GT4 configuration should have enough bandwidth to get full performance from a PCIe 3.0 x4 SSD but a GT2 configuration could end up throttling such a device In order to determine whether the Sylake NUC6i5SYK is affected by the OPI capabilities it is essential to understand the board design and the way each of the peripheral ports connect to the CPU The above block diagram should be considered in conjunction with the Skylake PCH-LP high-speed I/O (HSIO) configuration options depicted below One of the x4 links multiplexed with a SATA lane is used for the M.2 22x42,80 SSD slot One of the PCIe lanes that gets multiplexed with GbE is connected to the Intel I-219V Ethernet Adapter. and yet another PCIe lane is used for the WLAN adapter The important aspect to note here is that any M.2 SSD can have full PCIe 3.0 x4 connectivity to the Sunrise Point-LP PCH Intel's current technical documentation (PDF) for the Skylake NUC board mentions that the maximum possible performance for any M.2 SSD is around 1600 MBps The Samsung SSD 950 PRO and SM951 PCIe 3.0 x4 NVMe SSDs claim performance numbers in excess of 2000 MBps This obviously means that there is a bottleneck between the Skylake CPU and the Sunrise Point-LP Intel's Skylake-U/-Y reference designs are optimized for lower power and default the OPI to GT2 rates In the development of the NUC6i5SY product family the Intel team utilized the reference designs and default settings for the OPI and GT2 rates PCIe 3.0 x4 SSDs connected to the M.2 port of the NUC6i5SYK (BIOS v0042) are effectively limited to PCIe 2.0 x4 rates This throttling makes sense for battery-operated devices like 2-in-1s not so much for UCFF desktops like the NUCs After we brought this to Intel's attention the development team decided to complete the necessary changes and validation to support the maximum PCIe 3.0 performance Intel sent over a development BIOS (v1142) that turned on the higher performance OPI GT4 rate This BIOS is scheduled to be made public before the end of May 2016 (after completion of internal validation) The rest of this review deals with two major aspects - a quantitative measurement of the effectiveness of different types of SSDs in the Skylake NUC and an evaluation of the improvements resulting from ramping up the OPI to GT4 rates (i.e a comparison of the performance using BIOS v0042 and BIOS v1142) we processed various benchmarks while keeping everything other than the M.2 SSD and the BIOS version constant The various benchmarks presented in the next few sections were all processed with the M.2 SSD as the primary drive The drive was initialized with two partitions The primary OS partition was set to be 120GB in size while the remaining space was allocated to the secondary partition Both of the partitions were formatted in NTFS with default settings we will first take a look at the specifications of the four M.2 SSDs that were evaluated in the NUC6i5SYK along with CrystalDiskMark scores for each in both the BIOS versions we move on to real-world benchmarks - SYSmark 2014 PCMark 8 Storage Bench and a slightly tweaked AnandTech DAS Suite we take a look at a few miscellaneous aspects - power consumption believes he witnessed the inflection point three years ago with Skylake The "bad quality assurance of Skylake" was responsible for Apple finally making the decision to ditch Intel and focus on its own ARM-based processors for high-performance machines That's the claim made by outspoken former Intel principal engineer It's been one of the big stories from this last week; Apple finally announcing its two-year transition away from Intel for its Mac desktop and notebook lines There has been a lot of speculation about why this has happened with the main consideration being that it's aiming to consolidate the architectures across all its different platforms and finally into its laptop and desktop range That makes complete sense from a business and an architectural point of view but while it's something Piednoël says was always under consideration by Apple he believes if the company hadn't found so many issues within the Skylake architecture it would still be onboard the Intel chip train It was the straw that broke the Apple's back "The quality assurance of Skylake was more than a problem," says Piednoël during a casual Xplane chat and stream session We were getting way too much citing for little things inside Skylake Basically our buddies at Apple became the number one filer of problems in the architecture "When your customer starts finding almost as much bugs as you found yourself If that's true you can certainly see why the polo neck-wearing Apple contingent might have started getting a lot more serious about how it could effectively switch both its entire engineering and manufacturing over to ARM but also the entire Mac software ecosystem too Apple must have really hated Skylake… But, at the recent VLSI Technology and Circuits conference Intel CTO Mike Mayberry has pointed out separately that QA is a matter of scale With enterprise and exascale customers they're going to be working with far more chips than a company like Intel will check in-house And in that instance it's not unlikely for a customer to find bugs Keep up to date with the most important stories and the best deals Certainly at the time Piednoël seems convinced it was an extraordinary situation "For me this is the inflection point," says Piednoël "This is where the Apple guys who were always contemplating to switch they went and looked at it and said: 'Well we've probably got to do it.' Basically the bad quality assurance of Skylake is responsible for them to actually go away from the platform." It does have to be said that this is still just the publicly stated opinion of one former Intel engineer and can't necessarily be taken purely as fact and obviously isn't the only reason for Apple's switch either But Piednoël was always an interesting character while he was at Intel and a very outspoken one too often much to the chagrin of his PR handlers in front of us journalists But however much the quality assurance of the Skylake architecture did or didn't impact Apple's decision to switch wholesale over to ARM Dave JamesSocial Links NavigationEditor-in-Chief HardwareDave has been gaming since the days of Zaxxon and Lady Bug on the Colecovision and code books for the Commodore Vic 20 (Death Race 2000!) He built his first gaming PC at the tender age of 16 and finally finished bug-fixing the Cyrix-based system around a year later He first started writing for Official PlayStation Magazine and Xbox World many decades ago writing about the nightmarish graphics card market systems with Skylake or Kaby Lake processors can crash due to a bug that occurs when hyperthreading is enabled Intel has fixed the bug in a microcode update but until and unless you install the update the recommendation is that hyperthreading be disabled in the system firmware All Skylake and Kaby Lake processors appear to be affected, with one exception. While the brand-new Skylake-X chips still contain the flaw, their Kaby Lake X counterparts are listed by Intel as being fixed and unaffected with code that doesn't crash every single time Microcode updates can be sourced in two ways The system firmware can include new microcode that gets installed each time the system boots and operating systems can also update processor microcode through use of special (proprietary) drivers this typically means using packages from a distribution's "non-free" repository as no source code for these updates is available this means letting Windows Update do its job; Windows contains drivers for both AMD and Intel microcode updates Updated microcode drivers for Linux are available the Windows microcode driver does not appear to contain the fix Insider builds of Windows have a newer driver does not appear to include the updated microcode Although Microsoft does not appear to document which updates are included in each driver version the information is visible in a hex editor or similar tool; the Linux microcode updater includes four microcodes not found in the Windows driver including the ones necessary to address this problem a firmware fix—if available—is the best option does not appear to have a system firmware that includes the fix I don't mean to call out Microsoft specifically—I daresay many motherboard firmwares have similarly not been updated in the month and a half since Intel issued its patch—but rather to indicate that even systems that are still supported and do receive regular firmware updates may not have Intel's latest and greatest microcode yet On systems without either a firmware fix or updated driver disabling hyperthreading is believed to be a robust solution will probably just want to take their chances; the exact sequence of instructions and runtime conditions that cause problems seem to be rare (certainly rarer than Intel's description of the bug "Short Loops Which Use AH/BH/CH/DH Registers May Cause Unpredictable System Behavior," might otherwise indicate) affected systems appear to be stable anyway More than 18 months passed before this bug was fixed and there haven't been too many reports of Skylake machines crashing left and right because of it Eying up AMD systems as an alternative might be tempting, but they're susceptible to comparable issues, too in which certain sequences of instructions under certain system conditions can cause crashes or other misbehavior The workaround in AMD's case is to disable the micro-op cache Processors are certainly more reliable than software Intel provided us with lots of insights into Skylake the microarchitecture behind the 6th generation Core series processors Skylake marks the introduction of the Gen9 Intel HD Graphics technology In advance of our full Skylake architecture analysis (coming soon) I wanted to get a head start and explain the media side (including Quick Sync and the image processing pipeline) of Skylake in a separate piece Quick Sync has evolved through the last five years starting with limited hardware acceleration and usage of the programmable EU array in Sandy Bridge The second generation engine in Ivy Bridge moved to a hybrid hardware / software solution with rate control motion estimation and intra estimation as well as mode decision happening in the programmable EU array Usage of the EU array enabled tuning of the algorithms forward quantization and entropy coding were done in hardware in the MFX (multi-format codec engine) Haswell added JPEG / MJPEG decode to the MFX a dedicated VQE (video quality engine) for low power video processing and a faster media sampler we had the major transitions taking place in the video codec front - HEVC adoption was picking up In order to tackle these aspects and build on consumer feedback Intel made major updates to the media block / Quick Sync engine late last year Broadwell was also the first microarchitecture to support two BSDs (bit stream decoder) in the GT3 variants Each BSD allows a set of commands to decode one video stream Broadwell's updates (when compared to Haswell) are summarized in the slide below The detailed discussion of Broadwell's media capabilities above is relevant to the improvements made in Skylake The Gen9 graphics engine comes in multiple sizes for different power budgets the important aspect to note is that the media processing hardware (Media FF - Media Fixed Function) resides in the 'Unslice' While the GT2 comes with the minimum possible Media FF logic the GT3 and GT3e come with additional hardware capabilities This strategy is similar to what was adopted in Broadwell The Unslice can operate at a different voltage and frequency compared to the Slices This is especially important for video decoding / processing where the Media FF can run at higher clocks for better performance while ensuring minimal power consumption From the viewpoint of tools such as GPU-Z and HWiNFO it will be interesting to see if real-time statistics on voltage and clocks can be gathered for both the Unslice and the Slices power gating can be used at the Slices level or the EU group level Amongst the media improvements made in Skylake Intel classifies the Quick Sync modes in Broadwell and previous generations as 'PG-Mode' (Processor Graphics) It is optimized for faster than real-time encoding and flexibility 'FF-Mode' (Fixed Function) is optimized for real-time H.264 encoding with focus on lowering the latency and reducing the power consumption all other aspects of the encoding algorithm are handled in the MFX itself Since rate control is in the hands of the application software it is possible to do a 2-pass adaptive mode even with the FF hardware The new mode could possibly enable better user-experience with features such as Wi-Di Note that Skylake offers developers the flexibility to use either the PG mode or the FF mode in their applications PG mode still retains the TUx (Target Usage level) discussed in one of the above slides Skylake's MFX engine adds HEVC Main profile decode support (4Kp60 at up to 240 Mbps) Main10 decoding can be done with GPU acceleration The Quick Sync PG Mode supports HEVC encoding (again The DXVA Checker screenshot (taken on a i7-6700K a part with Intel HD Graphics 530 / GT2) for Skylake with driver version 10.18.15.4248 is produced below but it is done partially in the GPU (as specified in the slide above) VP8 DXVA profile doesn't seem to be activated yet There are new DXVA profiles (enabled) for the SVC (scalable video coding) extension to H.264 Additional improvements include a scalar and format converter (SFC) that can work with MFX and VQE (without using the EUs or the media sampler) This enables power-efficient rotation and color space conversion during media playback Yet another power-saving trick introduced in Skylake is the media memory bandwidth compression The compression is lossless and managed at the driver level Skylake's VQE also brings about new features with RAW image processing support (16-bit image pipeline) spatial denoising and local adaptive contrast enhancement (LACE) with claims of the VQE consuming less than 50mW during operation The new fixed function hardware in the performance-sensitive stages enables even low power mobile Skylake parts to support 4Kp60 RAW video processing LACE support is not available for 4K resolution on the Y-series Skylake parts Skylake can drive up to three simultaneous displays The supported resolutions are provided in the table below Intel was showing off the Skylake platform driving three 4K monitors simultaneously One of the disappointing aspects is the absence of a native HDMI 2.0 port with HDCP 2.2 support. Intel's solution is to add a LSPCon (Level Shifter - Protocol Converter) in the DP 1.2 path. Various solutions such as the MegaChips MCDP28 family of products exist for this purpose According to one of leaked Intel slides from earlier this year the Alpine Ridge Thunderbolt 3 controller can also act as a LSPCon and provide a HDMI 2.0 output Intel indicated that we could see Alpine Ridge supporting HDMI 2.0 towards the end of the year (something corroborated unofficially by a few motherboard manufacturers) The display sub-system also provides hardware support for Multi-plane Overlay (MPO) that allows alpha blending of multiple layers This saves power by selective disabling of un-needed planes Usage applications include certain video playback scenarios and HUD (heads-up display) gaming The table below lists out the updated support for MPO as one moves from Broadwell to Skylake The NV12 feature is particularly interesting from a media playback perspective - it is a video format that avoids conversion as video data moves between the decoder post-decoded NV12 content can also be provided directly to a MPO display plane and there is no need for the video post processor to do a NV12 to RGB conversion Intel indicated that the new Skylake MPO feature could save as much as 1.1W when playing back 1080p24 video on a 1440p panel - which is a substantial amount when mobile devices are considered Power savings are also achieved by altering the core display clock based on the display configuration number of displays and the resolution of each display Systems utilizing eDP with Windows 8.1 or later can also take advantage of hardware support for reducing refresh rate based on video content frame rate (for example 24 fps video streams can be played after reducing the panel refresh rate to 48 Hz - eliminating 3:2 pull-down issues while also providing power savings) Additional power saving can also be achieved on supported panels using Panel Self Refresh Media Buffer Optimization (PSR MBO) It is an Intel-developed optimization on top of the Panel Self Refresh feature of eDP 1.3 The media-related changes in Skylake's Gen9 GPU are best summarized by the slide below Skylake brings a lot of benefits to content creators - particularly in terms of improvements to Quick Sync and additional image processing options (including real-time 4Kp60 RAW import) While the additional video post processing options (such as LACE for adaptive contrast enhancement) can improve quality of video playback and the increase in graphics prowess can possibly translate to better madVR capabilities The first one is the absence of full hardware acceleration for HEVC Main10 decode Netflix has opted to go with HEVC Main10 for its 4K streams When Netflix finally enables 4K streaming on PCs unfortunately is not going to be as power efficient a platform as it could have been The second is the absence of a native HDMI 2.0 / HDCP 2.2 video output Even though a LSPCon solution is suggested by Intel Sinks supporting this standard have become quite affordable one can get a 4K Hisense TV with HDMI 2.0 / HDCP 2.2 capability Skylake is not going to deliver the most cost-effective platform to utilize the full capabilities of such a display Intel has added three new microprocessors for embedded and highly-integrated applications into its lineup The new CPUs are based on the Skylake microarchitecture and feature high-performance integrated graphics cores with an added eDRAM cache called Crystal Well The new products should offer high performance in memory bandwidth applications due to Skylake’s updated 2nd generation cache architecture The chips that Intel has added to its price list are the Core i7-6785R The new processors are designed to fit in all-in-one PCs small form-factor and other types of highly-integrated PCs that can satisfy the 65W TDP over the mobile Crystal Well variants that run at 45W The new desktop chips from Intel are based on the Skylake-H silicon in its most advanced configuration: with four general-purpose cores as well as the GT4e integrated graphics Not all the specifications of the processors are known at this point but we are talking about quad-core processors with Generation 9 Iris Pro graphics and 72 execution units (as well as 128 MB of eDRAM) a dual-channel DDR4-2133 memory controller a PCI Express 3.0 interface and three display outputs The power consumption of Intel’s new embedded products for desktops does not exceed 65 W and offer a potential upgrade path by OEMs for any equivalent systems that used an equivalent Broadwell-based R-series processor Intel unveiled its Skylake-H silicon in its full glory earlier this year when it released its mobile Xeon E3 v5 processors with the Iris Pro Graphics P580.  Several makers of industrial computer modules (such as Congatec) already use chips like the Intel Xeon E3-1515M v5 for their products The die of the Skylake-H processor looks rather long and the lion’s portion of its transistor budget was spent on the mammoth iGPU and the silicon underneath the CPU is the chipset (it's the Y/U series CPUs that have integrated chipsets) The new parts feature higher clock rates compared to the Broadwell processors although slightly lower than their K series counterparts The processors have a number of important architectural improvements which will affect the performance of these CPUs in real-world applications. It is interesting to note that Intel retained the full L3 cache size in its new R-series CPUs: in the Broadwell models part of the L3 was used for eDRAM tags but the new Skylake parts are now in line with their i7 and i5 naming due to the way the eDRAM is implemented This means that the i7-6785R has 8 MB of L3 Intel’s Skylake processors feature an upgraded microarchitecture with better parallelism and improved IPC, which means better performance almost across-the-board. An important capability of Skylake is its Speed Shift technology which can quickly increase frequency for a short amount of time in a bid to rapidly perform an operation (~1-3 milliseconds rather than 30-100 without Speed Shift) thus providing better user experience and ultimately saving power Intel’s Speed Shift requires support by the operating system and right now Microsoft’s Windows 10 can take advantage of the technology in a bid to improve its responsiveness.  Another important aspect of Intel’s Skylake CPUs with high-end iGPUs is their eDRAM which means the processors also gain the code name 'Crystal Well' The eDRAM for Skylake is different to that found in previous Crystal Well implementations: in the last generation the eDRAM acted as a victim cache to the L3 cache meaning that evicted cache lines from L3 would add up in the eDRAM and be quick for re-reading without having to access main memory The downside to this is that data could not end up in eDRAM without being used first giving initial data read latencies the same performance as previous processors Ultimately this is still good for graphics and gaming where textures are re-read from memory frequently The new arrangement for the eDRAM in these Skylake processors has placed the eDRAM in a different part of the chain between the System Agent and the DDR memory This means that the eDRAM acts as a DRAM buffer with 50 GBps bandwidth in each direction to the LLC but is also accessible for early reads/writes by any device that needs memory access through the system agent (i.e but now it means that Skylake's eDRAM implementation should offer a speedup in many more scenarios that before.  The final noteworthy improvement of the Skylake processors compared to previous-generation offerings is revamped graphics core as well as increased amount of execution units. Based on our findings last year real-world performance of Intel's high-end Iris Pro 6200 graphics core (Broadwell’s top iGPU) is higher than that of entry-level discrete graphics cards the highest-performing GT4e graphics core of Intel Skylake contains 72 EUs up from 48 in the case of the Broadwell Compute performance of Intel's contemporary top-of-the-range iGPU (Iris Pro 580) is around 1.1 TFLOPS depending on its frequency this one should be tangibly faster than its predecessor Skylake’s iGPU has a revamped multimedia engine which supports hardware decoding and encoding of UHD videos using HEVC or VP9 codecs and Core i5-6585R are already available at a tray price of $370 Partners of the chipmaker will likely use the new processors to build their new systems in the coming months Image Sources: Congatec, Intel's IDF presentations 2019 at 2:34 pm PTPatch reader and photographer Tim Yeager captured these Lake Elsinore sunset photographs in Tuscany Hills in the last week (Tim Yeager)Patch reader and photographer Tim Yeager captured these Lake Elsinore sunset photographs in Tuscany Hills in the last week CA — Patch reader Tim Yeager captured these images of sunsets from Tuscany Hills in Lake Elsinore on two different nights this week "We may not have many fall colors in the trees just look up right after sunset!" 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When Intel launched its new high-end desktop platform a few weeks ago we were provided with Core-X CPUs from quad cores on the latest Kaby Lake microarchitecture and 6/8/10 core parts on the Skylake-SP microarchitecture derived from the enterprise line and taking a different route to how the cache was structured over Skylake-S At the time we were told that these latter parts would be joined by bigger SKUs all the way up to 18 cores Intel was tight lipped on the CPU specifications until today The original Skylake-X processors up to 10 cores used Intel’s LCC silicon one of the three silicon designs typically employed in the enterprise space have historically been reserved for server CPUs and big money – if you wanted all the cores So the fact that Intel is introducing HCC silicon into the consumer desktop market is a change in strategy which many analysts say is due to AMD’s decision to bring their 16-core silicon into the market Both the new HCC-based processors and the recently released LCC-based processors will share the same LGA2066 socket as used on X299 motherboards and all the processors will differ in core count with slight variations on core frequencies the higher-end CPUs get a kick up in TDP to 165W to account for more cores and the frequency that these CPUs are running at The top Core i9-7980XE SKU will have a base frequency of 2.6 GHz but a turbo of 4.2 GHz The turbo will be limited to 2 cores of load however Intel has not listed the ‘all-core turbo’ frequencies which are often above the base frequencies It will be interesting to see how much power the top SKU will draw One question over the launch of these SKUs was regarding how much they would impinge into Intel’s Xeon line of processors We had already earmarked the Xeon Gold 6154/6150 as possible contenders for the high-end CPU and taking the price out of the comparison they can be quite evenly matched (the Xeons have a lower turbo The Xeons also come with multi-socket support and more DRAM channels Comparing against AMD’s Threadripper gives the following: We fully expect the review embargoes to be on the launch dates for each CPU Time to start ringing around to see if my sample was lost in the post Due to some sleuthing, PCGamer managed to obtain turbo frequencies based on per-core loading I'm surprised Intel doesn't give this data out like candy when the products are announced Previously at AnandTech we have been able to provide deep dives into what exactly is going on in the belly of the beast although the launch of Skylake has posed a fair share of problems Nominally we rely on a certain amount of openness from the processor/SoC manufacturer in providing low level details that we can verify and/or explain this information has typically been provided in advance of the launch by way of several meetings/consultations with discussions talking to the engineers means that it will remain a mystery until Pandora’s box is opened In the lead up to the launch of Intel’s Skylake platform architecture details have been both thin on the ground and thin in the air even when it comes down to fundamental details about the EU counts of the integrated graphics or explanations regarding the change in processor naming scheme we’ve been told to wait until Intel’s Developer Forum in mid-August for the main reason that the launch today is not the full stack Skylake launch which will take place later in the quarter Both Ryan and I will be at IDF taking fastidious notes and asking questions for everyone but at this point in time a good portion of our analysis comes from information provided by sources other than Intel we can't fully verify it as we normally would the details on the following few pages have been formed through investigation discussion and collaboration outside the normal channels and may be updated as more information is discovered or confirmed Some of this information is mirrored in our other coverage in order to offer a complete picture in each article as well After IDF we plan to put together a more detailed architecture piece as a fundamental block in analyzing our end results the best image of the underlying processor architecture is the block diagram: we discussed the DDR3L/DDR4 dual memory controller design on the previous page so we won’t go over it again here On the PCI-Express Graphics allocation side the Skylake processors will have sixteen PCIe 3.0 lanes to use for directly attached devices to the processor similar to Intel's previous generation processors These can be split into a single PCIe 3.0 x16 x8/x8 or x8/x4/x4 with basic motherboard design (Note that this is different to early reports of Skylake having 20 PCIe 3.0 lanes for GPUs If a motherboard supports x8/x4/x4 and a PCIe card is placed into that bottom slot SLI will not work because only one GPU will have eight lanes NVIDIA requires a minimum of PCIe x8 in order to enable SLI which makes the possible configurations interesting Below we discuss that the chipset has 20 (!) PCIe 3.0 lanes to use in five sets of four lanes and these could be used for graphics cards as well That means a motherboard can support x8/x8 from the CPU and PCIe 3.0 x4 from the chipset and end up with either dual-SLI or tri-CFX enabled when all the slots are populated The processor is connected to the chipset by the four-lane DMI 3.0 interface The DMI 3.0 protocol is an upgrade over the previous generation which used DMI 2.0 – this upgrade boosts the speed from 5.0 GT/s (2GB/sec) to 8.0 GT/s (~3.93GB/sec) essentially upgrading DMI from PCIe 2 to PCIe 3 but requires the motherboard traces between the CPU and chipset to be shorter (7 inches rather than 8 inches) in order to maintain signal speed and integrity This also allows one of the biggest upgrades to the system with Skylake the situation changes as compared to Haswell voltage regulation was performed by the motherboard and the right voltages were then put into the processor This was deemed inefficient for power consumption and for the Haswell/Broadwell processors Intel decided to create a fully integrated voltage regulator (FIVR) in order to reduce motherboard cost and reduce power consumption This had an unintended side-effect – while it was more efficient (good for mobile platforms) it also acted as a source of heat generation inside the CPU with high frequencies overclocking was limited by temperatures and the quality of the FIVR led to a large variation in results the voltage regulation is moved back into the hands of the motherboard manufacturers This should allow for cooler processors depending on how the silicon works but it will result in slightly more expensive motherboards A slight indication of this will be that some motherboards will go back to having a large amount of multiplexed phases on the motherboard and it will allow some manufacturers to use this as a differentiating point although the usefulness of such a design is sometimes questionable TrendingCommercialSouth FloridaAPrivate equity landlord drops $10M for Palm Beach Gardens apartmentsMarlena Demenus is selling off her New York portfolio and buying assets in South Florida In the aftermath of the controversial rent reform laws in New York City at least one property owner has decided to sell off assets in the city and focus on South Florida purchased 29 units at multifamily properties in Palm Beach Gardens for $9.92 million Sky Lake bought 19 units at the Legacy Place at 1000 Legacy Place and 10 units at Alton Townhomes at 8072-8110 Hobbes Way Sky Lake bought the Alton townhomes from developer Kolter Group while it purchased the units at Legacy Place from New York-based Bhansali Equities according to Compass Commercial’s Brad Kuskin The purchase price broke down to $341,000 per unit The units range from one to four bedrooms and the owner plans to rent out the properties SIGN UPThe move is part of Demenus’ decision to completely sell off her entire $34.7 million portfolio of New York properties which include apartments in Harlem and the Bronx Demenus is buying properties in Florida in part because the state has more favorable tax laws compared to New York Some high net worth individuals are moving to the Sunshine State after President Trump’s 2017 tax legislation capped the amount wealthy individuals in high tax states can deduct Sky Lake’s first deal in South Florida was a $14.75 million purchase at the Residences at Latitude Delray Beach where it plans to convert the apartment complex to annual rentals Sky Lake is a private equity firm specializing in multifamily and mixed-use real estate investments, according to Demenus’ LinkedIn page. Sky Lake recently sold nine buildings in New York City The new 6th Generation Skylake platform from Intel has launched today and as part of the package there are two new processors a new Z170 motherboard chipset with corresponding motherboards The purpose of the Skylake platform launch is to update the mainstream PC market segment for the purposes of better performance and enhanced connectivity Skylake is a new processor architecture based on Intel’s 14nm process using the newest generation of their FinFET lithographic technology and the two overclockable K series CPUs are the first processors to be released into the wild given that Intel launched Broadwell for desktop (a die shrink "tick" from 22nm to 14nm) only a couple of months ago Broadwell has only acted as a minor stopgap measure fulfilling the requirements of an upgradable platform and taking the crown of the best integrated graphics processor for a socket a number of users will see Skylake more as an upgrade from Haswell the last mainstream processor family that had a long market shelf life details about Skylake have been relatively rare to come by even in Intel’s own press documents and we are set to hear more details at Intel’s Developer Forum in mid-August we have been able to determine that Skylake has a raft of updates focusing on fixed function hardware to accelerate certain workloads as well as decoupling the CPU and PCIe frequency domains on the silicon to allow for more precise overclocking Skylake is not an earth shattering leap in performance we saw a 5.7% increase in performance over a Haswell processor at the same clockspeed and ~ 25% gains over Sandy Bridge That 5.7% value masks the fact that between Haswell and Skylake marking a 5.7% increase for a two generation gap at 3GHz Skylake actually performs worse than Haswell at an equivalent clockspeed We don’t have much from Intel as to analyze the architecture to see why this happens and it is pretty arguable that it is noticeable Hopefully this is just a teething issue with the new platform When we ratchet the CPUs back up to their regular the i7-6700K is an average 37% faster than Sandy Bridge in CPU benchmarks and 5% faster than the Devil’s Canyon based i7-4790K and Google Octane get substantially bigger gains suggesting that Skylake’s strengths may lie in fixed function hardware under the hood In full speed gaming benchmarks we have some situations that benefit from Skylake (GRID on high end graphics cards) and others that drop (Mordor on GTX 770) but the important aspect to consider is despite Skylake supporting both DDR3L and DDR4 memory our results show that even with a fast DDR3 kit a default-speed DDR4 set of memory is still worth upgrading to On average there’s a small change in performance in favor of the DDR4 (especially in integrated graphics) but DDR4 confers benefits such as more memory per module and lower voltages to aid power consumption A quick turn to the overclocking situation on Skylake: from our small sample set most of the CPUs achieved 4.6 GHz when pushing and 4.5 GHz comfortably including the retail sample that had 4.5 GHz their results match us or even slightly better our own with one report of a 5.0 GHz gem of a processor Skylake seems to have more of a temperature barrier than a voltage barrier so increasing the cooling seems to be the task of the day here to get the high frequencies A large number of users invested into Intel based platforms during the Core 2 Quad Sandy Bridge was notable because it inferred a large performance gain at stock speeds and with a good processor anyone could reach 4.7 GHz and even higher using a good high end cooler Intel has had a problem enticing these users to upgrade because their performance has been constantly matched by Ivy Bridge Haswell and Broadwell – for every 5% IPC increase from the CPU an average 200 MHz was lost on the good overclock and they would have to find a good overclocking CPU again apart from chipset functionality to upgrade From a clock-to-clock performance perspective Skylake gives an average ~25% better performance in CPU based benchmarks and when running both generations of processors at their stock speeds that increase jumps up to 37% it is even higher.  When you scale up to a 4.5 GHz Skylake against a 4.7 GHz Sandy Bridge the 4% frequency difference is only a tiny portion of that such as the move to a DDR4 memory topology that has denser memory modules as well as PCIe storage and even PCIe 3.0 graphics connectivity Skylake is not necessarily the most ground breaking architecture over Haswell It affords a 19% CPU performance gain over the i7-4770K and 5% over the i7-4790K There is a small minor issue with gaming that disappears when you use synthetics but only to the tune of a couple of percentage points chipset and DDR4 should be an intrigue in the minds of Sandy Bridge (and older) owners Next on the list for us is Intel’s Developer Forum in mid-August Here Intel has said they will present details on their Skylake architecture and it will hopefully shed some further insight into what is going on under the hood with Skylake We will have a full write up for you after the event There is still the rest of the Skylake stack to be released – non overclocking processors There is no official date on these except ‘later in the year’ We will also get to these when we have more information On the graphics side of the equation, the information comes in two loaded barrels. For the media capabilities, including information regarding Multi Plane Overlay, Intel’s Quick Sync and HEVC decode, head on over to Ganesh’s great one page summary Some of that information might be reproduced on this page to help explain some of the more esoteric aspects of the design First let us look at how Intel’s integrated graphics has progressed over the generations It has been no secret that the drive to integrated graphics has eaten almost all of the low end graphics market save one or two cards for extra monitor outputs this means slowly substituting a larger portion of the die to more execution units as well as upgrading how those units process data.  From the graphics above Gen9 takes Gen8’s concept but with an added element at the top – GT4 the eDRAM will come in 64 MB arrangements for GT3e (Iris) Intel’s graphics topology consists of an ‘unslice’ (or slice common) that deals solely with command streaming where each slice holds three sub-slices of 8 EUs scalar and format converter (SFC) and a multi format codec engine (MFX) Intel has both the name of the graphics used as well as the base/turbo frequencies of the graphics To synchronize both the name and the execution unit arrangement At this point we have no confirmation of any parts having the GT1.5 arrangement nor are we going to see any 23/24 EU combinations for Pentium/Celeron models similar to what we saw in Haswell.  For the 12 EU arrangements this means that these have a single slice of 24 EUs but half of them are disabled.  We questioned Intel on this back with Haswell regarding of the EU cuts are split to 4/4/4 from the 8/8/8 sub-slice arrangement and the answer we got back was interesting – there is no set pattern for 12 EU arrangements as long as the performance is in line with what is expected and the EU count per sub-slice cannot be user probed Despite the fact that a 3/3/6 arrangement might have L2 cache pressure in some circumstances Intel feels that at this level of performance they can guarantee that the processors they ship will be consistent Part of Intel’s strategy with the graphics is to separate all of these out as much as possible to different frequency planes and power gating allowing parts of the silicon to only be powered when needed or to offer more efficiency for regular use cases such as watching video The geometry pipe in the un-slice is improved to improve the triangle cull rate as well as remove redundant vertices which aids an improved tessellated that creates geometry in a format (tri-stips) that can be resubmitted through the triangle cull when needed Gen 9 graphics also features lossless image compression allowing for fewer data transfers across the graphics subsystem and an upgrade to the display controller allows the image format to be read in a compressed format so as not to uncompress it before it gets sent out to the display 16-bit support has been a key element to discrete graphics in 2014 and 2015 affording faster processing when less accuracy is required by dumping extra significant digits resulting in less power consumption for the same amount of work – Intel is exposing this to a greater degree in Gen9 for its shaders Intel’s big push on power for low-power Skylake is part of the reason why we did not see much difference in our Skylake-K review Being able to shut off more parts of the processor that are not in use allows the available power budget to be applied to those that need it hence why both power gating and frequency domains on the silicon contribute to power saving overall or allow work to complete quicker in a race to sleep environment One of the features I’m most particularly interested in is Multiplane Overlay a user might be looking at content that is stretched the image information is loaded into memory siphoned off to the graphics to perform the mathematics moved back into memory and then fired off to the display controller This in and out of the DRAM costs power and battery life so an attempt to mitigate this with fixed function hardware is ultimately beneficial This slides shows a good way on how MPO works The current implementation splits the screen into three ‘planes’ (app or any combination therein) which are fired off to the desktop window manager (DWM) these layers are worked on separately before being composited and sent off to the display (the top model) each of the planes fills a buffer in fixed function hardware on the display controller without touching the GPU and requiring it to be put into a high power mode MPO also allows for data in NV12 format to be processed on the fly as well rather than requiring it all to be RGB before it is recombined into the final image (which again and there is no z-hierarchy meaning that if an app is obscured by another but still requires work and then it does not get discarded as it should For non-OS work that takes full-screen environments it also requires the necessary hooks to the FF hardware otherwise it will assume it all as one plane and go back through the GPU Intel is planning to improve this feature over time Intel’s data showed a 17% power saving increase overall while watching a 1080p24 video on a 1440p panel Given the march to higher resolution displays and the lack of high resolution content I can imagine this being an important player in future content consumption or multitasking If you read our review of the Skylake-K processors you will note that in terms of clock-for-clock performance Skylake was not as big of a jump as people were perhaps expecting affording an average of 5.7% over Haswell and 2.7% over Broadwell users (us included) have come to expect a 5-10% generation on generation increase at the same frequency we started to point some fingers and questions at Intel regarding the architecture due to the fact that in a change from previous launches this information was to be provided post-launch.  That time was IDF and while Intel did get somewhat technical there are still some questions hanging in the air this is what we learned.  For this page we’re focusing purely on performance with power considerations a few pages further on There are many different metrics and underlying on-paper ways to increase performance Being able to process commands and data in fewer cycles or by handling/processing more data at once are two very important ones.  Intel tries to tackle both within the out-of-order architecture Instruction level parallelism is one of the holy grails in processor design – if you are able to separate a set of code into X instructions and process all X at once (due to a lack of dependencies) The downside is that a lot of code and as a result The best bit about an out-of-order architecture is that when many different branches of code and instructions are in flight at once they can be grouped up in the scheduler and a level of instruction parallelism can be achieved This allows the micro-ops (Intel’s version of deconstructing the instructions) to fill the queue and be arranged such that more parallelism can take place This also takes advantage of in-flight loads and stores such that data can be available by the time the micro-op gets to the front of that queue.  The idea is that heavy workloads that are interchangeable but require data access stalls can take advantage and hide the latency associated with those stalls as well as allowing certain operations to be fused in order to reduce the workload Intel has upgraded the front end of the IA core to allow a dispatch of six micro-ops at once but also the dispatch of micro-ops from the queue to the execution units has increased to six also Note that the execution units are limited by the number of INT/FP/Load/Store available so it is the job of the queue to reorder the micro-ops to take advantage of this The front-end (uOp allocation and up) is designed to take advantage of better branch prediction and faster prefetch as well as the increased in-flight buffers as mentioned above Branch prediction is also another element to increasing processor performance here – in some circumstances the CPU will speculate as to the instruction required and then dump the result it doesn’t need but not enough will result in increased processing time and latency So the branch predictor acts as a secret sauce for a lot of core design but we are told that Skylake improves this there are some small adjustments in the execution units with regards latency – the divider is improved which is normally a difficult set of commands to optimize and calculated via an improved radix Typically when writing scientific calculation code for example it is often suggested to minimize divisions where possible the FMUL (floating point multiply) has increased in latency over Broadwell We are told that this is due to design decisions that allows for better performance when it comes to creating enterprise silicon which is an interesting explanation in itself.  The execution units also have a greater degree of granularity in their power modes One element we did not mention in our original Skylake review (because we didn’t notice is that the L2 cache on Skylake is reduced from an 8-way associative cache to a 4-way model this relates to how the L2 data is stored and accessed where a doubling in the associativity often reduces the miss rate depending on the algorithm reducing the associativity saves power on data accesses that are successful and in some circumstances can also save area on the silicon die.  So by moving from 8-way to 4-way Intel saves some power with Skylake but loses some performance if you compare two identical silicon models Intel counters this move by saying that the bandwidth to the L2 cache misses is doubled as well as improving how cache and page misses are handled providing a lower latency for that data.  The end result should be performance similar to that in Haswell We were also told that this has benefits when designing the server processor line although we will have to wait and see exactly why Another element to the back-end results in improved HyperThreading performance where for example the ratio of Cinebench single threaded performance to multi-threaded performance was better than previous generations Part of the HT improvements relate to micro-op retirement – basically being able to abandon used operations and free up the execution queue my first question was if instruction retirement was ever a bottleneck – would you ever be in a position where you have all the data you need to process an instruction but because the older instruction is not cleared and the new design allows each thread in a core to retire four micro-ops in one cycle This should mean that HyperThreading yields some tangible benefits when it comes to intensive workloads (again another nod to the enterprise performance crowd) Skylake looks a lot like Haswell with minor tweaks that are not instantaneously obvious It can be hard to feel how ‘a deeper buffer’ can increase performance when the software being used barely filled the buffer in the first place A lot of these improvements are aimed directly at the pure-performance perspective (except L2 and FMUL to an extent) so you really have to be gunning it or have a specific workload to take advantage although other information needs to be investigated A side note on the enterprise based comments In the first slide of the core front/back end it states ‘dedicated server and client IP configurations’ this is a drive to make Intel’s processor/core designs more modular in nature such that being able to produce a custom processor for a certain enterprise market is easier to do designing a core and working within design constraints can be a pain (you want registers and caches to be close to the queues to be close to the execution units and so on) so some optimization in a modular system still has to be made It also makes us wonder to what level the modularity can take and if some of the more esoteric designs might help Intel develop custom SoCs similar to AMD Intel is introducing both SGX (Security Guard Extensions) and MPX (Memory Protection Extensions) to Skylake This is in part similar to ARM’s TrustZone whereby a program can be run in its own environment (or enclave is what Intel calls it) where it cannot interact outside the enclave and any attempt by other programs to access the memory in which it resides fails The MPX implementation is to aid buffer overflow errors that are a common source of security breaches Gallery: Intel SGX and MPX Until testing Broadwell-H and meeting up with certain individuals at IDF, the principle of the eDRAM Intel had been using was a little ill-defined. Sure we tested it when it launched, as well as the Broadwell processors and commented that the obvious tasks to be improved came down to gaming on integrated graphics or very specific workloads.  For Skylake eDRAM enabled processors will be configured differently to previous versions in order to make the effect of the eDRAM more seamless for software This is the current eDRAM representation for Haswell and Broadwell processors Here we see that the eDRAM is accessed by a store of L4 tags contained within the LLC of each core and as a result acts more as a victim cache to the L3 rather than as a dynamic random access memory implementation Any instructions or hardware that requires data from the eDRAM has to go through the LLC and do the L4 tag conversion limiting its potential (although speeding up certain specific workloads by virtue of a 50 GB/s per-link bi-directional interface the eDRAM becomes a DRAM buffer and automatically transparent to any software (CPU or IGP) that requires DRAM access other hardware that communicates through the system agent (such as PCIe devices or data from the chipset) and requires information in DRAM does not need to navigate through the L3 cache on the processor.  Technically graphics workloads still need to circle around the system agent but GPU drivers need not worry about the size of the eDRAM when it becomes buffer-esque and is accessed before the memory controller is adjusted into a higher power read request The underlying message is that the eDRAM is now observed by all DRAM accesses allowing it to be fully coherent and no need for it to be flushed to maintain that coherence it can bypass the L3 when required in a standard DRAM access scenario While the purpose of the eDRAM is to be as seamless as possible Intel is allowing some level on control at the driver level allowing textures larger than the L3 to reside only in eDRAM in order to prevent overwriting the data contained in the L3 and having to recache it for other workloads the eDRAM from Intel will come in two flavors – 64 MB and 128 MB which is different to the 128 MB only policy for Haswell and Broadwell Back when Intel was discussing eDRAM before this it was noted that Intel considered 32 MB ‘enough’ but doubled it and doubled it again just to make sure the system truly saw some benefit It seems that for some circumstances (or some price points for that matter) 64 MB is felt as a better fit in that regard given that Intel believes that its initial design had plenty of headroom.  As far as we can tell eDRAM will be available in 64MB for GT3e and 128MB for GT4e configurations (48 EUs and 72 EUs respectively) although we might see some variation as time goes on We have confirmed with Intel that the 64 MB implementation is a half-silicon implementation (rather than a disabled full-silicon) but the bandwidth to the system agent is the same in both circumstances A number of media have already been requesting an announcement regarding a discrete processor with an eDRAM implementation I even enjoyed conversations at IDF where it was suggested that Intel could produce an i7 at 4.0 GHz with 128MB eDRAM we were told that a quad core desktop part with eDRAM (either 4+2e or 4+4e) is currently not POR because technically a 3+2 is not on their ‘plan of record) having been mentioned as not POR means means that Intel has looked at it as an option but at this time has not decided to release it at this time - if they ever will is another question to ask Intel For users who actively want an LGA1151 4+4e configuration make sure your Intel representative knows it because customer requests travel up the chain In the wake of Skylake-X's introduction and disappointing results from our overclocking attempts we put a lot of thought into the power and thermal issues plaguing Intel's highest-end desktop CPUs These roadblocks boil down to a couple of salient points that we'd like to explore in as much depth as possible: (1) Skylake-X at its stock settings can barely be cooled during normal operation This is due to its power consumption being extremely high in some situations and its thermal paste keeping waste heat from being dissipated effectively.(2) There’s barely any room for enthusiasts to overclock many motherboards limit Skylake-X CPUs further due to poor design choices Those looking for high overclocks need not apply we decided to grab one of the simpler LGA 2066 motherboards out there build a bench table capable of supporting vertical operation and start running Core i9-7900X through more tests we examined thermal sensor readings and where they were reporting heat we compared our infrared thermal measurements around the motherboard's LGA interface and VRMs to double-check the sensors' plausibility This also allowed us to document the warm-up phase and how heat spread via time-lapse videos we’re interested to know if and how other on-board components are affected by the processor-imposed hot-spots We’re using the most current version of our motherboard’s BIOS to guarantee reliable sensor readings The new beta version of HWiNFO (v5.53-3190) was chosen for the same reasons The motherboard's CPU power supply employs a total of 5+1 phases realized by an International Rectifier IR35201 dual-loop buck controller It officially supports Intel’s VR12.5 Rev 1.5 Kudos if you counted more regulator circuits; doubling of five phases allows two circuits per phase reducing each VRM's load and spreading hot-spots out more evenly Each circuit has its own 60A IR3555 PowIRstage. These highly integrated chips combine the necessary gate drivers the IR3555 is able to read analog values for the built-in temperature sensor how is it possible to also determine the temperature of hot-spots on the PCB without an IR camera handy MSI uses Nuvoton's NCT6795D Super I/O chip which is able to collect and report a wide variety of sensor readings One of these readings comes from a thermistor (see picture below) placed among the PowIRstage chips This is why we chose the spot right underneath this thermistor as the location for our video-based measurements we'll check temperatures on the regulator circuits’ chokes and capacitors as well as board temperatures all the way to the CPU It’s important to understand that motherboard manufacturers deliberately add certain safety mechanisms to their designs One example from our test platform is that a Skylake-X processor’s clock rate throttles to exactly 1.2 GHz if the thermistor reports a temperature of 105°C or more (see the MOS line in the image below) That frequency is maintained until the temperature drops under 90°C Only then does it restore the processor’s full speed Even though the board material’s flashpoint (FR4) is significantly higher than 105°C the recommended maximum temperatures for continued operation is between 95 and 105°C or hairline fractures in the conductor paths This safety-consciousness is a welcome trend Enthusiasts using Intel’s Extreme Tuning Utility (XTU) can find this setting under Thermal Throttling: Yes Without the corresponding MOSFETs with temperature sensor output (mostly as voltage) the IR35201 buck controller provides its own temperature readings it was supposedly possible to read voltage converter temperatures as VRM1 and VRM2 for graphics cards with certain PWM controllers the temperature values weren’t determined by temperature sensors because the MOSFETs being used didn't have sensors inside we get the reported values from within the PowIRstage the values under VR T1 and VR T2 are significantly higher than we'd expect The PWM controller can only guarantee a stable and safe power supply if all components stays within its technical specifications This means that a maximum temperature setting is necessary XTU’s Motherboard VR Throttling: Yes setting turns yellow and the CPU’s frequency throttles to 1.2 GHz the motherboard simply shuts down to avoid hardware damage It estimates the temperatures for its cores and package based on readings from different integrated digital temperature sensors (DTS) The precision of those estimates increases as the sensors get hotter If the core or package temperature gets too hot The package temperature includes the integrated voltage regulator’s leakage currents The IVR is responsible for providing different voltages to subsystems within the CPU High overclocks and manual voltage increases can cause the temperature limit to be exceeded unexpectedly Tools might not be able to reliably capture this effect which means that the CPU might throttle without any reason that would be visible to the user Observation #1: It’s well-known that the CPU might throttle its clock rate due to its core or package temperatures being too high the Super I/O chip might also throttle it due to VRM temperatures being too high the PWM controller can also cause throttling if it gets too hot since this could result in a dangerously unstable power supply it’s an urban legend that the PWM controller can report VRM temperatures MORE: CPU Overclocking Guide: How (and Why) to Tweak Your Processor MORE: Intel & AMD Processor Hierarchy MORE: All CPUs Content Delidded AMD Ryzen 9 9950X3D runs 23 degrees cooler PC enthusiast delidded a 9950X3D using fishing line and a clothes iron empowering Huawei to define global standards There are days in this profession in which I am surprised The longer I stay in the technology industry There are several reasons to be surprised: someone comes out of the blue with a revolutionary product and the ecosystem/infrastructure to back it up or a company goes above and beyond a recent mediocre pace to take on the incumbents (with or without significant financial backing) as to why such a product would ever be thought of and another is seeing how one company reacts to another We’ve been expecting the next high-end desktop version of Skylake for almost 18 months now and fully expected it to be an iterative update over Broadwell-E: a couple more cores Intel has surprised us with at least two of the reasons above: Skylake-X will increase the core count of Intel’s HEDT platform from 10 to 18 The Skylake-X announcement is a lot to unpack and there are several elements to the equation Let’s start with familiar territory: the first half of the processor launch The last generation, Broadwell-E offered four processors: two six-core parts The main difference between the two six-core parts was the PCIe lane count and aside from the hike in pricing for the top-end SKU these were iterative updates over Haswell-E: two more cores for the top processor This strategy from Intel is derived from what they call internally as their ‘LCC’ core The enterprise line from Intel has three designs for their silicon – a low core count All the processors in the enterprise line are typically made from these three silicon maps: a 10-core LCC silicon die can have two cores disabled to be an 8-core Or a 22-core XCC die can have all but four cores disabled but still retain access to all the L3 cache to have an XCC processor that has a massive cache structure the processors made public were all derived from the LCC silicon The first half of the Skylake-X processor llineup follows this trend Intel will launch four Skylake-X processors based on the LCC die which for this platform will have a maximum of 12 cores This design will not feature Intel’s new ‘favored core’ Turbo 3.0 technology (more on that below) This processor will be the entry level model for any user who needs the benefit of quad-channel memory but perhaps doesn’t need a two-digit number of cores or has a more limited budget which hits a potential sweet spot in the LCC design with the highest LCC base clock of 3.6 GHz and the joint-highest turbo settings: 4.3 GHz for regular turbo and 4.5 GHz for favored core this CPU gets support for DDR4-2666 memory However in another break from Intel’s regular strategy Normally only the lowest CPU of the HEDT stack would be adjusted in this way but Intel is using the PCIe lane allocation as another differentiator as a user considers which processor in the stack to go for we would expect it to be competing directly against AMD’s Ryzen 7 1800X which will be the equivalent of a generation behind in IPC but $100 cheaper Right now the Core i9-7900X is the only Core i9 with any details: this is a ten core processor a 4.3 GHz turbo and a 4.5 GHz favored core it will support DDR4-2666 and has a TDP of 140W so this 10-core part runs in at a $999 tray price ($1049 retail likely) One brain cell to twitch when reading this specification is the price we expected the top SKU for 10-cores to be $999 due to the way the enterprise processors were priced the new pricing scheme is somewhat scrapped again which is what we expected the Broadwell-E based Core i7-6950X to be but the pricing comes back down to reasonable levels Meanwhile for the initial launch of Skylake-X the final processor in this stack is the Core i9-7920X This processor will be coming out later in the year but it will be a 12-core processor on the same LGA2066 socket for $1199 (retail ~$1279) We are told that Intel is still validating the frequencies of this CPU to find a good balance of performance and power although we understand that it might be 165W rather than 140W as Intel’s pre-briefing explained that the whole X299 motherboard set should be ready to support 165W processors Intel has always had that processor that consumed more power than the rest This was usually called the ‘workstation’ processor designed to be in a single or dual socket design but with a pumped up frequency and price to match In order for Intel to provide this 12-core processor to customers There’s a chance that not all the factors are in place yet especially if they come out with a 12-core part that is clocked high and could potentially absorb some of their enterprise sales Given the expected timing and launch for this processor, as mentioned we were expecting mid-summer, that would have normally put the crosshairs into Intel’s annual IDF conference in mid-August, although that conference has now been canned There are a few gaming events around that time to which Intel may decide to align the launch to.